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v5.7
ProASICPLUS(R)
(R)
Flash Family FPGAs
High Performance Routing Hierarchy
* * * * * * * * * * * * * * * * *
(R)
Features and Benefits
High Capacity
Commercial and Industrial
* * * * * * * * * * * * 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os 300, 000 to 1 million System Gates 72 k to 198 kbits of Two Port SRAM 158 to 712 User I/Os 0.22 m 4 LM Flash-Based CMOS Process Live At Power-Up (LAPU) Level 0 Support Single-Chip Solution No Configuration Device Required Retains Programmed Design during Power-Down/Up Cycles Mil/Aero Devices Operate over Full Military Temperature Range 3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military temperature) Two Integrated PLLs External System Performance up to 150 MHz The Industry's Most Effective Security Key (FlashLock ) Low Impedance Flash Switches Segmented Hierarchical Routing Structure Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells
APA075 75,000 3,072 27 k 12 2 2 4 24 158 Yes Yes 100, 144 208 - 144 APA150 150,000 6,144 36k 16 2 2 4 32 242 Yes Yes 100 208 456 144, 256
Ultra-Fast Local and Long-Line Network High-Speed Very Long-Line Network High-Performance, Low Skew, Splittable Global Network 100% Routability and Utilization Schmitt-Trigger Option on Every Input 2.5 V/3.3 V Support with Individually-Selectable Voltage and Slew Rate Bidirectional Global I/Os Compliance with PCI Specification Revision 2.2 Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant Pin Compatible Packages across the ProASICPLUS Family PLL with Flexible Phase, Multiply/Divide and Delay Capabilities Internal and/or External Dynamic PLL Configuration Two LVPECL Differential Pairs for Clock or Data Inputs Flexibility with Choice of Industry-Standard Front-End Tools Efficient Design through Front-End Timing and Gate Optimization In-System Programming (ISP) via JTAG Port SmartGen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical)
I/O
Military
Reprogrammable Flash Technology
Unique Clock Conditioning Circuitry
Standard FPGA and ASIC Design Flow ISP Support SRAMs and FIFOs
*
Performance
* * * * * * *
Secure Programming Low Power
Table 1 * ProASICPLUS Product Profile
Device Maximum System Gates Tiles (Registers) Embedded RAM Bits (k=1,024 bits) Embedded RAM Blocks (256x9) LVPECL PLL Global Networks Maximum Clocks Maximum User I/Os JTAG ISP PCI Package (by pin count) TQFP PQFP PBGA FBGA CQFP2 CCGA/LGA2 Notes: APA3001 300,000 8,192 72 k 32 2 2 4 32 290 Yes Yes - 208 456 144, 256 208, 352 APA450 450,000 12,288 108 k 48 2 2 4 48 344 Yes Yes - 208 456 144, 256, 484 APA6001 600,000 21,504 126 k 56 2 2 4 56 454 Yes Yes - 208 456 256, 484, 676 208, 352 624 APA750 750,000 32,768 144 k 64 2 2 4 64 562 Yes Yes - 208 456 676, 896 APA10001 1,000,000 56,320 198 k 88 2 2 4 88 712 Yes Yes - 208 456 896, 1152 208, 352 624
1. Available as Commercial/Industrial and Military/MIL-STD-883B devices. 2. These packages are available only for Military/MIL-STD-883B devices.
S e pt em be r 2 0 08 (c) 2008 Actel Corporation
i See the Actel website for the latest version of the datasheet.
ProASICPLUS Flash Family FPGAs
Ordering Information
APA1000 _ F FG G 1152 I Application (Ambient Temperature Range) Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) PP = Pre-production ES = Engineering Silicon (Room Temperature Only) M = Military (-55C to 125C) B = MIL-STD-883 Class B Package Lead Count Lead-free packaging Blank = Standard Packaging G = RoHS Compliant Packaging Package Type TQ = Thin Quad Flat Pack (0.5 mm pitch) PQ = Plastic Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) BG = Plastic Ball Grid Array (1.27 mm pitch) CQ = Ceramic Quad Flat Pack (1.05 mm pitch) CG = Ceramic Column Grid Array (1.27 mm pitch) LG = Land Grid Array (1.27 mm pitch) Speed Grade Blank = Standard Speed F = 20% Slower than Standard Part Number APA075 APA150 APA300 APA450 APA600 APA750 APA1000 = = = = = = = 75,000 Equivalent System Gates 150,000 Equivalent System Gates 300,000 Equivalent System Gates 450,000 Equivalent System Gates 600,000 Equivalent System Gates 750,000 Equivalent System Gates 1,000,000 Equivalent System Gates
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ProASICPLUS Flash Family FPGAs
Device Resources
User I/Os2 Commercial/Industrial
Military/MIL-STD-883B CCGA/ LGA TQFP TQFP PQFP PBGA FBGA FBGA FBGA FBGA FBGA FBGA CQFP CQFP 100-Pin 144-Pin 208-Pin 456-Pin 144-Pin 256-Pin 484-Pin 676-Pin 896-Pin 1152-Pin 208-Pin 352-Pin 624-Pin
Device
APA075 APA150 APA300 APA450 APA600 APA750 APA1000
66 66
107
158 158 158 4 158 158
4
100 242 290 4 344 356
4
100 100 4 100
186 3 186 3, 4 186 186
3
158 344
3
248 248 248 440 440
3, 4
370 3
454 454 562 5 642 4, 5 712 5
158 158
158 158 4
356 356 4
Notes: 1. Package Definitions: TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array, CQFP = Ceramic Quad Flat Pack, CCGA = Ceramic Column Grid Array, LGA = Land Grid Array 2. Each pair of PECL I/Os is counted as one user I/O. 3. FG256 and FG484 are footprint-compatible packages. 4. Military Temperature Plastic Package Offering 5. FG896 and FG1152 are footprint-compatible packages.
General Guideline
Maximum performance numbers in this datasheet are based on characterized data. Actel does not guarantee performance beyond the limits specified within the datasheet.
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ProASICPLUS Flash Family FPGAs
Temperature Grade Offerings
Package TQ100 TQ144 PQ208 BG456 FG144 FG256 FG484 FG676 FG896 FG1152 CQ208 CQ352 CG624 Note: C = Commercial I = Industrial M = Military B = MIL-STD-883 M, B M, B M, B M, B M, B C, I APA075 C, I C, I C, I C, I C, I C, I C, I C, I, M C, I, M C, I, M C, I, M C, I C, I C, I C, I C, I C, I, M C, I, M C, I, M C, I C, I C, I, M C, I M, B M, B M, B C, I, M C, I, M C, I C, I C, I, M C, I, M APA150 C, I APA300 APA450 APA600 APA750 APA1000
Speed Grade and Temperature Matrix
-F C I M, B Note: C = Commercial I = Industrial M = Military B = MIL-STD-883 Std.
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ProASICPLUS Flash Family FPGAs
Table of Contents
General Description
ProASICPLUS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Timing Control and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Sample Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Adjustable Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Clock Skew Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 Calculating Typical Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 Tristate Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42 Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Predicted Global Routing Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 1-46 1-48 1-50
Global Routing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50 Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 Sample Macrocell Library Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 Embedded Memory Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-73 Recommended Design Practice for VPN/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-74
Package Pin Assignments
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 352-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 456-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69 624-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
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ProASICPLUS Flash Family FPGAs
General Description
The ProASICPLUS family of devices, Actel's secondgeneration Flash FPGAs, offers enhanced performance over Actel's ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile Flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, the ProASICPLUS family offers a unique clock conditioning circuit based on two on-board phase-locked loops (PLLs). The family offers up to one million system gates, supported with up to 198 kbits of two-port SRAM and up to 712 user I/Os, all providing 50 MHz PCI performance. Advantages to the designer extend beyond performance. Unlike SRAM-based FPGAs, four levels of routing hierarchy simplify routing, while the use of Flash technology allows all functionality to be live at powerup. No external boot PROM is required to support device programming. While on-board security mechanisms prevent access to the program information, reprogramming can be performed in-system to support future design iterations and field upgrades. The device's architecture mitigates the complexity of ASIC migration at higher user volume. This makes ProASICPLUS a costeffective solution for applications in the networking, communications, computing, and avionics markets. The ProASICPLUS family achieves its nonvolatility and reprogrammability through an advanced Flash-based 0.22 m LVCMOS process with four layers of metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs. This results in predictable performance compatible with gate arrays. The ProASICPLUS architecture provides granularity comparable to gate arrays. The device core consists of a Sea-of-TilesTM. Each tile can be configured as a flip-flop, latch, or three-input/one-output logic function by programming the appropriate Flash switches. The combination of fine granularity, flexible routing resources, and abundant Flash switches allow 100% utilization and over 95% routability for highly congested designs. Tiles and larger functions are interconnected through a four-level routing hierarchy. Embedded two-port SRAM blocks with built-in FIFO/RAM control logic can have user-defined depths and widths. Users can also select programming for synchronous or asynchronous operation, as well as parity generations or checking. The unique clock conditioning circuitry in each device includes two clock conditioning blocks. Each block provides a PLL core, delay lines, phase shifts (0 and 180), and clock multipliers/dividers, as well as the circuitry needed to provide bidirectional access to the PLL. The PLL block contains four programmable frequency dividers which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. The clock conditioning circuit also delays or advances the incoming reference clock up to 8 ns (in increments of 0.25 ns). The PLL can be configured internally or externally during operation without redesigning or reprogramming the part. In addition to the PLL, there are two LVPECL differential input pairs to accommodate high-speed clock and data inputs. To support customer needs for more comprehensive, lower-cost, board-level testing, Actel's ProASICPLUS devices are fully compatible with IEEE Standard 1149.1 for test access port and boundary-scan test architecture. For more information concerning the Flash FPGA implementation, please refer to the "Boundary Scan (JTAG)" section on page 1-11. ProASICPLUS devices are available in a variety of highperformance plastic packages. Those packages and the performance features discussed above are described in more detail in the following sections.
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ProASICPLUS Flash Family FPGAs
ProASICPLUS Architecture
The proprietary ProASICPLUS architecture granularity comparable to gate arrays. provides The ProASICPLUS device core consists of a Sea-of-Tiles (Figure 1-1). Each tile can be configured as a three-input logic function (e.g., NAND gate, D-Flip-Flop, etc.) by programming the appropriate Flash switch interconnections (Figure 1-2 and Figure 1-3 on page 1-3). Tiles and larger functions are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Flash switches are programmed to connect signal lines to
the appropriate logic cell inputs and outputs. Dedicated high-performance lines are connected as needed for fast, low-skew global signal distribution throughout the core. Maximum core utilization is possible for virtually any design. ProASICPLUS devices also contain embedded, two-port SRAM blocks with built-in FIFO/RAM control logic. Programming options include synchronous or asynchronous operation, two-port RAM configurations, user defined depth and width, and parity generation or checking. Please see the "Embedded Memory Configurations" section on page 1-22 for more information.
RAM Block 256x9 Two-Port SRAM or FIFO Block
I/Os
Logic Tile RAM Block 256x9 Two Port SRAM or FIFO Block
Figure 1-1 * The ProASICPLUS Device Architecture
Floating Gate
Switch In
Sensing
Switching
Word Switch Out
Figure 1-2 * Flash Switch
1 -2
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ProASICPLUS Flash Family FPGAs
Local Routing In 1 Efficient Long-Line Routing
In 2 (CLK)
In 3 (Reset)
Figure 1-3 * Core Logic Tile
Live at Power-Up
The Actel Flash-based ProASIC devices support Level 0 of the live at power-up (LAPU) classification standard. This feature helps in system component initialization, executing critical tasks before the processor wakes up, setting up and configuring memory blocks, clock generation, and bus activity management. The LAPU feature of Flash-based ProASICPLUS devices greatly simplifies total system design and reduces total system cost, often eliminating the need for Complex Programmable Logic Device (CPLD) and clock generation PLLs that are used for this purpose in a system. In addition, glitches and brownouts in system power will not corrupt the ProASICPLUS device's Flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASICPLUS devices simplify total system design, and reduce cost and design risk, while increasing system reliability and improving system initialization time.
PLUS
Flash Switch
Unlike SRAM FPGAs, ProASICPLUS uses a live-on-power-up ISP Flash switch as its programming element. In the ProASICPLUS Flash switch, two transistors share the floating gate, which stores the programming information. One is the sensing transistor, which is only used for writing and verification of the floating gate voltage. The other is the switching transistor. It can be used in the architecture to connect/separate routing nets or to configure logic. It is also used to erase the floating gate (Figure 1-2 on page 1-2).
Logic Tile
The logic tile cell (Figure 1-3) has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra-fast local and efficient long-line routing resources). Any three-input, one-output logic function (except a three-input XOR) can be configured as one tile. The tile can be configured as a latch with clear or set or as a flip-flop with clear or set. Thus, the tiles can flexibly map logic and sequential gates of a design.
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ProASICPLUS Flash Family FPGAs
Routing Resources
The routing structure of ProASICPLUS devices is designed to provide high performance through a flexible fourlevel hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high-speed, very long-line resources, and high performance global networks. The ultra-fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles (Figure 1-4). The efficient long-line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASICPLUS device (Figure 1-5 on page 1-5). Each tile can drive signals onto the efficient long-line resources, which can in turn access every input of every tile. Active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout. The high-speed, very long-line resources, which span the entire device with minimal delay, are used to route very long or very high fanout nets. (Figure 1-6 on page 1-6). The high-performance global networks are low-skew, high fanout nets that are accessible from external pins or from internal logic (Figure 1-7 on page 1-7). These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically with signals accessing every input on all tiles.
L
L
L
L
Inputs
L
Output
L
Ultra-Fast Local Lines (connects a tile to the adjacent tile, I/O buffer, or memory block)
L
L
L
Figure 1-4 * Ultra-Fast Local Resources
1 -4
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ProASICPLUS Flash Family FPGAs
Spans 4 Tiles
Spans 2 Tiles
Spans 1 Tile
Logic Tile
L L L L L L
L
L
L
L
L
L
L
L
L
L
L
L
Spans 1 Tile Spans 2 Tiles Spans 4 Tiles
L
L
L
L
L
L
Logic Cell
L L L L L L
Figure 1-5 * Efficient Long-Line Resources
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ProASICPLUS Flash Family FPGAs
High Speed Very Long-Line Resouces PAD RING
SRAM
PAD RING
I/O RING
I/O RING
SRAM
PAD RING
Figure 1-6 * High-Speed, Very Long-Line Resources
Clock Resources
The family offers powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has two clock conditioning blocks containing a phase-locked loop (PLL) core, delay lines, phase shifter (0 and 180), clock multiplier/dividers, and all the circuitry needed for the selection and interconnection of inputs to the global network (thus providing bidirectional access to the PLL). This permits the PLL block to drive inputs and/or outputs via the two global lines on each side of the chip (four total lines). This circuitry is discussed in more detail in the "ProASICPLUS Clock Management System" section on page 1-13. ProASICPLUS
Clock Trees
One of the main architectural benefits of ProASICPLUS is the set of power- and delay-friendly global networks. ProASICPLUS offers four global trees. Each of these trees is based on a network of spines and ribs that reach all the tiles in their regions (Figure 1-7 on page 1-7). This flexible clock tree architecture allows users to map up to 88 different internal/external clocks in an APA1000 device. Details on the clock spines and various numbers of the family are given in Table 1-1 on page 1-7. The flexible use of the ProASICPLUS clock spine allows the designer to cope with several design requirements. Users implementing clock-resource intensive applications can easily route external or gated internal clocks using global routing spines. Users can also drastically reduce delay penalties and save buffering resources by mapping critical high fanout nets to spines. For design hints on using these features, refer to Actel's Efficient Use of ProASIC Clock Trees application note.
1 -6
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ProASICPLUS Flash Family FPGAs
High-Performance Global Network
PAD RING
PAD RING
I/O RING
Top Spine
Global Networks
Global Pads
Global Pads Global Spine Global Ribs
Bottom Spine
I/O RING
Scope of Spine (Shaded area plus local RAMs and I/Os)
PAD RING
Note: This figure shows routing for only one global path. Figure 1-7 * High-Performance Global Network Table 1-1 * Clock Spines APA075 Global Clock Networks (Trees) Clock Spines/Tree Total Spines Top or Bottom Spine Height (Tiles) Tiles in Each Top or Bottom Spine Total Tiles 4 6 24 16 512 3,072 APA150 4 8 32 24 768 6,144 APA300 4 8 32 32 1,024 8,192 APA450 4 12 48 32 1,024 12,288 APA600 4 14 56 48 1,536 21,504 APA750 4 16 64 64 2,048 32,768 APA1000 4 22 88 80 2,560 56,320
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ProASICPLUS Flash Family FPGAs
Array Coordinates
During many place-and-route operations in Actel's Designer software tool, it is possible to set constraints that require array coordinates. Table 1-2 is provided as a reference. The array coordinates are measured from the lower left (0,0). They can be used in region constraints for specific groups of core cells, I/Os, and RAM blocks. Wild cards are also allowed. I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed because there is not a one-to-one correspondence between I/O
Table 1-2 * Array Coordinates Logic Tile Min. Device APA075 APA150 APA300 APA450 APA600 APA750 APA1000 x 1 1 1 1 1 1 1 y 1 1 5 5 5 5 5 x 96 128 128 192 224 256 352 Max. y 32 48 68 68 100 132 164 Bottom y - - (1,1) or (1,3) (1,1) or (1,3) (1,1) or (1,3) (1,1) or (1,3) (1,1) or (1,3) Memory Rows Top y (33,33) or (33, 35) (49,49) or (49, 51) (69,69) or (69, 71) (69,69) or (69, 71) (101,101) or (101, 103) (133,133) or (133, 135) (165,165) or (165, 167) Min. 0,0 0,0 0,0 0,0 0,0 0,0 0,0 All Max. 97, 37 129, 53 129, 73 193, 73 225, 105 257, 137 353, 169
cells and core cells. In addition, the I/O coordinate system changes depending on the die/package combination. Core cell coordinates start at the lower left corner (represented as (1,1)) or at (1,5) if memory blocks are present at the bottom. Memory coordinates use the same system and are indicated in Table 1-2. The memory coordinates for an APA1000 are illustrated in Figure 1-8. For more information on how to use constraints, see the Designer User's Guide or online help for ProASICPLUS software tools.
(1,169) (1,167) (1,165) (1,164)
Memory Blocks
(353,169) (352,167) (352,165) (352,164)
Core
(1,5) (1,3) (1,1) (0,0) Memory Blocks
(352,5) (352,3) (352,1) (353,0)
Figure 1-8 * Core Cell Coordinates for the APA1000
1 -8
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ProASICPLUS Flash Family FPGAs
Input/Output Blocks
To meet complex system demands, the ProASICPLUS family offers devices with a large number of user I/O pins, up to 712 on the APA1000. Table 1-3 shows the available supply voltage configurations (the PLL block uses an independent 2.5 V supply on the AVDD and AGND pins). All I/Os include ESD protection circuits. Each I/O has been tested to 2000 V to the human body model (per JESD22 (HBM)). Six or seven standard I/O pads are grouped with a GND pad and either a VDD (core power) or VDDP (I/O power) pad. Two reference bias signals circle the chip. One protects the cascaded output drivers, while the other creates a virtual VDD supply for the I/O ring. I/O pads are fully configurable to provide the maximum flexibility and speed. Each pad can be configured as an input, an output, a tristate driver, or a bidirectional buffer (Figure 1-9 and Table 1-4).
Table 1-3 *
ProASICPLUS I/O Power Supply Voltages VDDP 2.5 V 3.3 V 3.3 V 3.3 V
Input Compatibility Output Drive
2.5 V 2.5 V
3.3V/2.5V Signal Control Pull-up Control
Y EN A
Pad
3.3 V/2.5 V Signal Control Drive Strength and Slew-Rate Control
Figure 1-9 * I/O Block Schematic Representation
Table 1-4 * Function
I/O Features Description * * * Selectable 2.5 V or 3.3 V threshold levels Optional pull-up resistor Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be configured as an input only, not a bidirectional buffer. This input type may be slower than a standard input under certain conditions and has a typical hysteresis of 0.35 V. I/O macros with an "S" in the standard I/O library have added Schmitt capabilities. 3.3 V PCI Compliant (except Schmitt trigger inputs) Selectable 2.5 V or 3.3 V compliant output signals 2.5 V - JEDEC JESD 8-5 3.3 V - JEDEC JESD 8-A (LVTTL and LVCMOS) 3.3 V PCI compliant Ability to drive LVTTL and LVCMOS levels Selectable drive strengths Selectable slew rates Tristate Selectable 2.5 V or 3.3 V compliant output signals 2.5 V - JEDEC JESD 8-5 3.3 V - JEDEC JESD 8-A (LVTTL and LVCMOS) 3.3 V PCI compliant Optional pull-up resistor Selectable drive strengths Selectable slew rates Tristate
I/O pads configured as inputs
* I/O pads configured as outputs * * * * * * * * I/O pads configured as bidirectional * buffers * * * * * * *
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ProASICPLUS Flash Family FPGAs
Power-Up Sequencing
While ProASICPLUS devices are live at power-up, the order of VDD and VDDP power-up is important during system start-up. VDD should be powered up simultaneously with VDDP on ProASICPLUS devices. Failure to follow these guidelines may result in undesirable pin behavior during system start-up. For more information, refer to Actel's Power-Up Behavior of ProASICPLUS Devices application note.
low voltage differential amplifier) and a signal and its complement, PPECL (I/P) (PECLN) and NPECL (PECLREF). The LVPECL input pad cell differs from the standard I/O cell in that it is operated from VDD only. Since it is exclusively an input, it requires no output signal, output enable signal, or output configuration bits. As a special high-speed differential input, it also does not require pull ups. Recommended termination for LVPECL inputs is shown in Figure 1-10. The LVPECL pad cell compares voltages on the PPECL (I/P) pad (as illustrated in Figure 1-11) and the NPECL pad and sends the results to the global MUX (Figure 1-14 on page 1-14). This high-speed, low-skew output essentially controls the clock conditioning circuit. LVPECLs are designed to meet LVPECL JEDEC receiver standard levels (Table 1-5).
LVPECL Input Pads
In addition to standard I/O pads and power pads, ProASICPLUS devices have a single LVPECL input pad on both the east and west sides of the device, along with AVDD and AGND pins to power the PLL block. The LVPECL pad cell consists of an input buffer (containing a
PPECL
Z 0= 50
+ From LVPECL Driver Z 0= 50 NPECL R = 100 _ Data
Figure 1-10 * Recommended Termination for LVPECL Inputs
Voltage 2.72 2.125 1.49 0.86
Figure 1-11 * LVPECL High and Low Threshold Values Table 1-5 * Symbol VIH VIL VID LVPECL Receiver Specifications Parameter Input High Voltage Input Low Voltage Differential Input Voltage Min. 1.49 0.86 0.3 Max 2.72 2.125 VDD Units V V V
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ProASICPLUS Flash Family FPGAs
Boundary Scan (JTAG)
ProASICPLUS devices are compatible with IEEE Standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective, board-level testing. The basic ProASICPLUS boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers, and instruction register (Figure 1-12). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS) and the optional IDCODE instruction (Table 1-6). Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI and TDO (test data input and output), TMS (test mode selector) and TRST (test reset input). TMS, TDI and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These
pins are dedicated for boundary-scan test usage. Actel recommends that a nominal 20 k pull-up resistor is added to TDO and TCK pins. The TAP controller is a four-bit state machine (16 states) that operates as shown in Figure 1-13 on page 1-12. The '1's and `0's represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. ProASICPLUS devices have to be programmed at least once for complete boundary-scan functionality to be available. Prior to being programmed, EXTEST is not available. If boundary-scan functionality is required prior to programming, refer to online technical support on the Actel website and search for ProASICPLUS BSDL.
I/O
I/O
I/O
I/O
I/O Test Data Registers
TDI
TCK
TMS
TAP Controller
Instruction Register
Device Logic
TRST
TDO
I/O
I/O
I/O
I/O
I/O
Figure 1-12 * ProASICPLUS JTAG Boundary Scan Test Logic Circuit Table 1-6 * Boundary-Scan Opcodes Hex Opcode EXTEST SAMPLE/PRELOAD IDCODE 00 01 0F CLAMP BYPASS Table 1-6 * Boundary-Scan Opcodes Hex Opcode 05 FF
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I/O
I/O
I/O
I/O
Bypass Register
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ProASICPLUS Flash Family FPGAs
The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. The TRST pin may also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. ProASICPLUS devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register
with four fields (lowest significant byte (LSB), ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundaryscan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O.
1
Test-Logic Reset 0 Run-Test/ Idle 1 Select-DRScan 0 1 Capture-DR 0 0 1 Select-IRScan 0 1 Capture-IR 0 Shift-IR 1 1 0 Exit-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 0 1 1 0 1
0
Shift-DR
1 Exit-DR 0 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 0 1
Figure 1-13 * TAP Controller State Diagram
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ProASICPLUS Flash Family FPGAs
Timing Control and Characteristics
ProASICPLUS Clock Management System
ProASICPLUS devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASICPLUS family contains two phase-locked loop (PLL) blocks which perform the following functions: * * * * * * * * * Clock Phase Adjustment via Programmable Delay (250 ps steps from -7 ns to +8 ns) Clock Skew Minimization Clock Frequency Synthesis Input Frequency Range (fIN) = 1.5 to 180 MHz Feedback Frequency Range (fVCO) = 24 to 180 MHz Output Frequency Range (fOUT) = 8 to 180 MHz Output Phase Shift = 0 and 180 Output Duty Cycle = 50% Low Output Jitter (max at 25C) - - - fVCO <10 MHz. Jitter 1% or better 10 MHz < fVCO < 60 MHz. Jitter 2% or better fVCO > 60 MHz. Jitter 1% or better
follows (Figure 1-15 on page 1-15, Table 1-7 on page 115, and Table 1-8 on page 1-16):
Global A (secondary clock)
* * * * Output from Global MUX A Conditioned version of PLL output (fOUT) - delayed or advanced Divided version of either of the above Further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay)1 Output from Global MUX B Delayed or advanced version of fOUT Divided version of either of the above Further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay)2
Global B
* * * *
Each PLL has the following key features:
Functional Description
Each PLL block contains four programmable dividers as shown in Figure 1-14 on page 1-14. These allow frequency scaling of the input clock signal as follows: * * The n divider divides the input clock by integer factors from 1 to 32. The m divider in the feedback path allows multiplication of the input clock by integer factors ranging from 1 to 64. The two dividers together can implement any combination of multiplication and division resulting in a clock frequency between 24 and 180 MHz exiting the PLL core. This clock has a fixed 50% duty cycle. The output frequency of the PLL core is given by the formula EQ 1-1 (fREF is the reference clock frequency):
EQ 1-1
Note: Jitter(ps) = Jitter(%)* period For Example: Jitter in picoseconds at 100 MHz = 0.01 * (1/100E6) = 100 ps * Maximum Acquisition = 80 s for fVCO > 40 MHz Time = 30 s for fVCO < 40 MHz Low Power Consumption - 6.9 mW (max - analog supply) + 7.0W/MHz (max - digital supply) *
*
*
fOUT = fREF * m/n * The third and fourth dividers (u and v) permit the signals applied to the global network to each be further divided by integer factors ranging from 1 to 4.
Physical Implementation
Each side of the chip contains a clock conditioning circuit based on a 180 MHz PLL block (Figure 1-14 on page 114). Two global multiplexed lines extend along each side of the chip to provide bidirectional access to the PLL on that side (neither MUX can be connected to the opposite side's PLL). Each global line has optional LVPECL input pads (described below). The global lines may be driven by either the LVPECL global input pad or the outputs from the PLL block, or both. Each global line can be driven by a different output from the PLL. Unused global pins can be configured as regular I/Os or left unconnected. They default to an input with pull-up. The two signals available to drive the global networks are as
The implementations shown in EQ2 and EQ3 enable the user to define a wide range of frequency multiplier and divisors. fGLB = m/(n*u)
EQ 1-2
fGLA = m/(n*v)
EQ 1-3
1. This mode is available through the delay feature of the Global MUX driver.
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ProASICPLUS Flash Family FPGAs
enable the user to define a wide range of frequency multipliers and divisors. The clock conditioning circuit can advance or delay the clock up to 8 ns (in increments of 0.25 ns) relative to the positive edge of the incoming reference clock. The system also allows for the selection of output frequency clock phases of 0 and 180. Prior to the application of signals to the rib drivers, they pass through programmable delay units, one per global network. These units permit the delaying of global
signals relative to other signals to assist in the control of input set-up times. Not all possible combinations of input and output modes can be used. The degrees of freedom available in the bidirectional global pad system and in the clock conditioning circuit have been restricted. This avoids unnecessary and unwieldy design kit and software work.
AVDD
AGND
VDD
GND
Global MUX B OUT Input Pins to the PLL See Figure 1-15 + on page 1-14 External Feedback Signal Clock Conditioning Circuitry (Top level view)
GLA
GLB 27 4 Flash Configuration Bits Dynamic Configuration Bits
Global MUX A OUT 8
Clock Conditioning Circuitry Detailed Block Diagram CLK P+ PFIVDIV[4:0] /n PLL Core /m FBDIV[5:0] Clock from Core (GLINT mode) 0 1 EXTFB XDLYSEL
Deskew Delay 2.95 ns 2 3 1
Delay Line 0.25 ns to 4.00 ns, 16 steps, 0.25 ns increments
Bypass Primary 1 7 180 0 6 5 4 2
OBMUX[2:0]
0 /u OBDIV[1:0]
DLYB[1:0]
Delay Line 0.0 ns, 0.25 ns, 0.50 ns and 4.00 ns
GLB
3 OADIV[1:0] 2 1 OAMUX[1:0] /v DLYA[1:0]
Delay Line 0.0 ns, 0.25 ns, 0.50 ns and 4.00 ns
FBDLY[3:0] FBSEL[1:0]
GLA
CLKA Clock from Core (GLINT mode)
Bypass Secondary
Notes: 1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments. 2. DLYA and DLYB are programmable delay lines, each with selectable values 0 ps, 250 ps, 500 ps, and 4 ns. 3. OBDIV will also divide the phase-shift since it takes place after the PLL Core. Figure 1-14 * PLL Block - Top-Level View and Detailed PLL Block Diagram
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ProASICPLUS Flash Family FPGAs
Package Pins GL NPECL
Physical I/O Buffers Std. Pad Cell PECL Pad Cell
Global MUX Configuration Tile Global MUX B OUT
PPECL External Feedback Global MUX A OUT Configuration Tile
GLMX GL
Std. Pad Cell Std. Pad Cell
CORE
Legend Physical Pin DATA Signals to the Core DATA Signals to the PLL Block DATA Signals to the Global MUX Control Signals to the Global MUX
Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time. Figure 1-15 * Input Connectors to ProASICPLUS Clock Conditioning Circuitry Table 1-7 * MUX FBSEL 1 2 3 XDLYSEL 0 1 OBMUX 0 1 2 4 5 6 7 OAMUX 0 1 2 3 Primary bypass, no divider Primary bypass, use divider Delay Clock Using FBDLY Phase Shift Clock by 0 Reserved Phase Shift Clock by +180 Reserved GLA Secondary bypass, no divider Secondary bypass, use divider Delay Clock Using FBDLY Phase Shift Clock by 0 +0.25 to +4 ns in 0.25 ns increments +0.25 to +4 ns in 0.25 ns increments Feedback Unchanged Deskew feedback by advancing clock by system delay GLB Fixed delay of -2.95 ns Internal Feedback Internal Feedback and Advance Clock Using FBDLY External Feedback (EXTFB) -0.25 to -4 ns in 0.25 ns increments Clock-Conditioning Circuitry MUX Settings Datapath Comments
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ProASICPLUS Flash Family FPGAs
Table 1-8 * Delay Line DLYB 0 1 2 3 DLYA 0 1 2 3
Clock-Conditioning Circuitry Delay-Line Settings Delay Value (ns)
Sample Implementations
Frequency Synthesis
Figure 1-16 on page 1-17 illustrates an example where the PLL is used to multiply a 33 MHz external clock up to 133 MHz. Figure 1-17 on page 1-17 uses two dividers to synthesize a 50 MHz output clock from a 40 MHz input reference clock. The input frequency of 40 MHz is multiplied by five and divided by four, giving an output clock (GLB) frequency of 50 MHz. When dividers are used, a given ratio can be generated in multiple ways, allowing the user to stay within the operating frequency ranges of the PLL. For example, in this case the input divider could have been two and the output divider also two, giving us a division of the input frequency by four to go with the feedback loop division (effective multiplication) by five.
0 +0.25 +0.50 +4.0 0 +0.25 +0.50 +4.0
Lock Signal
An active-high Lock signal (added via the SmartGen PLL development tool) indicates that the PLL has locked to the incoming clock signal. The PLL will acquire and maintain lock even when there is jitter on the incoming clock signal. The PLL will maintain lock with an input jitter up to 5% of the input period, with a maximum of 5 ns. Users can employ the Lock signal as a soft reset of the logic driven by GLB and/or GLA. Note if FIN is not within specified frequencies, then both the FOUT and lock signal are indeterminate.
Adjustable Clock Delay
Figure 1-18 on page 1-18 illustrates the delay of the input clock by employing one of the adjustable delay lines. This is easily done in ProASICPLUS by bypassing the PLL core entirely and using the output delay line. Notice also that the output clock can be effectively advanced relative to the input clock by using the delay line in the feedback path. This is shown in Figure 1-19 on page 1-18.
PLL Configuration Options
The PLL can be configured during design (via Flashconfiguration bits set in the programming bitstream) or dynamically during device operation, thus eliminating the need to reprogram the device. The dynamic configuration bits are loaded into a serial-in/parallel-out shift register provided in the clock conditioning circuit. The shift register can be accessed either from user logic within the device or via the JTAG port. Another option is internal dynamic configuration via user-designed hardware. Refer to Actel's ProASICPLUS PLL Dynamic Reconfiguration Using JTAG application note for more information. For information on the clock conditioning circuit, refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note.
Clock Skew Minimization
Figure 1-20 on page 1-19 indicates how feedback from the clock network can be used to create minimal skew between the distributed clock network and the input clock. The input clock is fed to the reference clock input of the PLL. The output clock (GLA) feeds a clock network. The feedback input to the PLL uses a clock input delayed by a routing network. The PLL then adjusts the phase of the input clock to match the delayed clock, thus providing nearly zero effective skew between the two clocks. Refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note for more information.
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ProASICPLUS Flash Family FPGAs
Global MUX B OUT 33 MHz
/1 /n PLL Core /m /4
180 0
/u /1
D 133 MHz
GLB
D D External Feedback /v Global MUX A OUT D GLA
Figure 1-16 * Using the PLL 33 MHz In, 133 MHz Out
Global MUX B OUT 40 MHz
/4 /n PLL Core /m /5
180 0
/u /1
GLB D 50 MHz
D D External Feedback /v Global MUX A OUT D GLA
Figure 1-17 * Using the PLL 40 MHz In, 50 MHz Out
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ProASICPLUS Flash Family FPGAs
Global MUX B OUT 133 MHz
/1 /n PLL Core /m /1
180 0
/u /1
D 133 MHz
GLB
D D External Feedback /v Global MUX A OUT D GLA
Figure 1-18 * Using the PLL to Delay the Input Clock
Global MUX B OUT 133 MHz
/1 /n PLL Core /m /1
180 0
/u /1
GLB D 133 MHz
D D External Feedback /v Global MUX A OUT D GLA
Figure 1-19 * Using the PLL to Advance the Input Clock
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ProASICPLUS Flash Family FPGAs
Off chip
On chip
Global MUX B OUT
/1
/n
180
133 MHz
/m
PLL Core
0
/u
D
GL B
/1
D External Feedback D
133 MHz
/v D GL A
Global MUX A OUT
Reference clock
Q
SET
D
Q CLR
Figure 1-20 * Using the PLL for Clock Deskewing
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ProASICPLUS Flash Family FPGAs
Logic Tile Timing Characteristics
Timing characteristics for devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all ProASICPLUS family members. Internal routing delays are device dependent. Design dependency means that actual delays are not determined until after placement and routing of the user's design are complete. Delay values may then be determined by using the Timer utility or by performing simulation with post-layout delays. ProASICPLUS
Timing Derating
Since ProASICPLUS devices are manufactured with a CMOS process, device performance will vary with temperature, voltage, and process. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and optimal process variations. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case process variations (within process specifications). The derating factors shown in Table 1-9 should be applied to all timing data contained within this datasheet. All timing numbers listed in this datasheet represent sample timing characteristics of ProASICPLUS devices. Actual timing delay values are design-specific and can be derived from the Timer tool in Actel's Designer software after place-and-route.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing-critical paths. Critical nets are determined by net property assignment prior to place-and-route. Refer to the Actel Designer User's Guide or online help for details on using constraints.
Table 1-9 *
Temperature and Voltage Derating Factors (Normalized to Worst-Case Commercial, TJ = 70C, VDD = 2.3 V) -55C -40C 0.86 0.82 0.79 0C 0.91 0.87 0.83 25C 0.94 0.90 0.86 70C 1.00 0.95 0.91 85C 1.02 0.98 0.93 110C 1.05 1.01 0.96 125C 1.13 1.09 1.04 135C 1.18 1.13 1.08 150C 1.27 1.21 1.16
2.3 V 2.5 V 2.7 V Notes:
0.84 0.81 0.77
1. The user can set the junction temperature in Designer software to be any integer value in the range of -55C to 175C. 2. The user can set the core voltage in Designer software to be any value between 1.4 V and 1.6 V.
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ProASICPLUS Flash Family FPGAs
PLL Electrical Specifications
Parameter Frequency Ranges Reference Frequency fIN (min.) Reference Frequency fIN (max.) OSC Frequency fVCO (min.) OSC Frequency fVCO (max.) Clock Conditioning Circuitry fOUT (min.) Clock Conditioning Circuitry fOUT (max.) Long Term Jitter Peak-to-Peak Max.* Temperature fVCO<10 25C (or higher) 1% Frequency MHz 1060 1% Jitter(ps) = Jitter(%)*period For example: Jitter in picoseconds at 100 MHz = 0.01 * (1/100E6) = 100 ps 0C -40C -55C Acquisition Time from Cold Start Acquisition Time (max.) Acquisition Time (max.) Power Consumption Analog Supply Power (max.*) Digital Supply Current (max.) Duty Cycle Input Jitter Tolerance Note: *High clock frequencies (>60 MHz) under typical setup conditions 6.9 mW per PLL 7 W/MHz 50% 0.5% 5% input period (max. 5 ns) Maximum jitter allowable on an input clock to acquire and maintain lock. 30 s 80 s fVCO 40 MHz fVCO > 40 MHz 1.5% 2.5% 2.5% 2.5% 3.5% 3.5% 1% 1% 1% 1.5 MHz 180 MHz 24 MHz 180 MHz 6 MHz 180 MHz Clock conditioning circuitry (min.) lowest input frequency Clock conditioning circuitry (max.) highest input frequency Lowest output frequency voltage controlled oscillator Highest output frequency voltage controlled oscillator Lowest output frequency clock conditioning circuitry Highest output frequency clock conditioning circuitry Value Notes
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ProASICPLUS Flash Family FPGAs
(R)
User Security
devices have FlashLock protection bits that, once programmed, block the entire programmed contents from being read externally. Please refer to Table 1-10 for details on the number of bits in the key for each device. If locked, the user can only reprogram the device employing the user-defined security key. This protects the device from being read back and duplicated. Since programmed data is stored in nonvolatile memory cells (actually very small capacitors) rather than in the wiring, physical deconstruction cannot be used to compromise data. This type of security breach is further discouraged by the placement of the memory cells beneath the four metal layers (whose removal cannot be accomplished without disturbing the charge in the capacitor). This is the highest security provided in the industry. For more information, refer to Actel's Design Security in Nonvolatile Flash and Antifuse FPGAs white paper.
Table 1-10 * Flashlock Key Size by Device Device APA075 APA150 APA300 APA450 APA600 APA750 APA1000 Key Size 79 bits 79 bits 79 bits 119 bits 167 bits 191 bits 263 bits
Embedded Memory Configurations
The embedded memory in the ProASICPLUS family provides great configuration flexibility (Table 1-11). Each ProASICPLUS block is designed and optimized as a twoport memory (one read, one write). This provides 198 kbits of two-port and/or single port memory in the APA1000 device. Each memory block can be configured as FIFO or SRAM, with independent selection of synchronous or asynchronous read and write ports (Table 1-12). Additional characteristics include programmable flags as well as parity checking and generation. Figure 1-21 on page 1-24 and Figure 1-22 on page 1-25 show the block diagrams of the basic SRAM and FIFO blocks. Table 1-13 on page 1-24 and Table 1-14 on page 1-25 describe memory block SRAM and FIFO interface signals, respectively. A single memory block is designed to operate at up to 150 MHz (standard speed grade typical conditions). Each block is comprised of 256 9-bit words (one read port, one write port). The memory blocks may be cascaded in width and/or depth to create the desired memory organization. (Figure 1-23 on page 1-26). This provides optimal bit widths of 9 (one block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1,024. Refer to Actel's SmartGen User's Guide for more information. Figure 1-24 on page 1-26 gives an example of optimal memory usage. Ten blocks with 23,040 bits have been used to generate three arrays of various widths and depths. Figure 1-25 on page 1-26 shows how RAM blocks can be used in parallel to create extra read ports. In this example, using only 10 of the 88 available blocks of the APA1000 yields an effective 6,912 bits of multiple port RAM. The Actel SmartGen software facilitates building wider and deeper memory configurations for optimal memory usage.
ProASICPLUS
Embedded Memory Floorplan
The embedded memory is located across the top and bottom of the device in 256x9 blocks (Figure 1-1 on page 1-2). Depending on the device, up to 88 blocks are available to support a variety of memory configurations. Each block can be programmed as an independent memory array or combined (using dedicated memory routing resources) to form larger, more complex memory configurations. A single memory configuration could include blocks from both the top and bottom memory locations.
Table 1-11 * ProASICPLUS Memory Configurations by Device
Maximum Width Device APA075 APA150 APA300 APA450 APA600 APA750 APA1000 Bottom 0 0 16 24 28 32 44 Top 12 16 16 24 28 32 44 D 256 256 256 256 256 256 256 W 108 144 144 216 252 288 396
Maximum Depth D 1,536 2,048 2,048 3,072 3,584 4,096 5,632 W 9 9 9 9 9 9 9
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Table 1-12 * Basic Memory Configurations Type RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO Write Access Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous Read Access Asynchronous Asynchronous Synchronous Transparent Synchronous Transparent Synchronous Pipelined Synchronous Pipelined Asynchronous Asynchronous Synchronous Transparent Synchronous Transparent Synchronous Pipelined Synchronous Pipelined Asynchronous Asynchronous Synchronous Transparent Synchronous Transparent Synchronous Pipelined Synchronous Pipelined Asynchronous Asynchronous Synchronous Transparent Synchronous Transparent Synchronous Pipelined Synchronous Pipelined Parity Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Checked Generated Library Cell Name RAM256x9AA RAM256x9AAP RAM256x9AST RAM256x9ASTP RAM256x9ASR RAM256x9ASRP RAM256x9SA RAM256xSAP RAM256x9SST RAM256x9SSTP RAM256x9SSR RAM256x9SSRP FIFO256x9AA FIFO256x9AAP FIFO256x9AST FIFO256x9ASTP FIFO256x9ASR FIFO256x9ASRP FIFO256x9SA FIFO256x9SAP FIFO256x9SST FIFO256x9SSTP FIFO256x9SSR FIFO256x9SSRP
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ProASICPLUS Flash Family FPGAs
DI <0:8> WADDR <0:7> WRB WBLKB WCLKS WPE
SRAM (256x9) Sync Write and Sync Read Ports
DO <0:8> RADDR <0:7> RDB RBLKB RCLKS RPE
DI <0:8> WADDR <0:7> WRB WBLKB WPE
SRAM (256x9) Async Write and Async Read Ports
DO <0:8> RADDR <0:7> RDB RBLKB RCLKS RPE
PARODD DI <0:8> WADDR <0:7> WRB WBLKB WCLKS WPE DO <0:8> RADDR <0:7> RDB RBLKB DI <0:8> WADDR <0:7> WRB WBLKB
PARODD DO <0:8> RADDR <0:7> RDB RBLKB RCLKS RPE
SRAM (256x9) Sync Write and Async Read Ports
SRAM (256x9) Async Write and Sync Read Ports
RPE
WPE
PARODD
PARODD
Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when RAM blocks are cascaded and are automatically inserted by the software tools. Figure 1-21 * Example SRAM Block Diagrams Table 1-13 * Memory Block SRAM Interface Signals SRAM Signal WCLKS RCLKS RADDR<0:7> RBLKB RDB WADDR<0:7> WBLKB DI<0:8> WRB DO<0:8> RPE WPE PARODD Bits 1 1 8 1 1 8 1 9 1 9 1 1 1 In/Out In In In In In In In In In Out Out Out In Description Write clock used on synchronization on write side Read clock used on synchronization on read side Read address Read block select (active Low) Read pulse (active Low) Write address Write block select (active Low) Input data bits <0:8>, <8> can be used for parity In Write pulse (active Low) Output data bits <0:8>, <8> can be used for parity Out Read parity error (active High) Write parity error (active High) Selects Odd parity generation/detect when High, Even parity when Low
Note: Not all signals shown are used in all modes.
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ProASICPLUS Flash Family FPGAs
DI<0:8> LEVEL<0:7> LGDEP<0:2> WRB WBLKB RDB RBLKB PARODD WCLKS DO <0:8> FIFO (256x9) Sync Write and Sync Read Ports WPE RPE FULL EMPTY EQTH GEQTH RESET RCLKS
DI<0:8> LEVEL<0:7> LGDEP<0:2> WRB WBLKB RDB RBLKB PARODD WCLKS FIFO (256x9) Sync Write and Async Read Ports
DO <0:8> WPE RPE FULL EMPTY EQTH GEQTH RESET
DI <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB RDB RBLKB PARODD
DO <0:8> FIFO (256x9) WPE RPE FULL EMPTY EQTH GEQTH RESET RCLKS
DI <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB
DO <0:8> FIFO (256x9) WPE Async Write and Async Read Ports RPE FULL EMPTY EQTH GEQTH RESET
Async Write and Sync Read Ports
RDB RBLKB PARODD
Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when RAM blocks are cascaded and are automatically inserted by the software tools. Figure 1-22 * Basic FIFO Block Diagrams Table 1-14 * Memory Block FIFO Interface Signals FIFO Signal WCLKS RCLKS LEVEL <0:7> RBLKB RDB RESET WBLKB DI<0:8> WRB FULL, EMPTY EQTH, GEQTH DO<0:8> RPE WPE LGDEP <0:2> PARODD Bits 1 1 8 1 1 1 1 9 1 2 2 9 1 1 3 1 In/Out In In In In In In In In In Out Out Out Out Out In In Description Write clock used for synchronization on write side Read clock used for synchronization on read side Direct configuration implements static flag logic Read block select (active Low) Read pulse (active Low) Reset for FIFO pointers (active Low) Write block select (active Low) Input data bits <0:8>, <8> will be generated parity if PARGEN is true Write pulse (active Low) FIFO flags. FULL prevents write and EMPTY prevents read EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more Output data bits <0:8>. <8> will be parity output if PARGEN is true. Read parity error (active High) Write parity error (active High) Configures DEPTH of the FIFO to 2 (LGDEP+1) Parity generation/detect - Even when Low, Odd when High
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ProASICPLUS Flash Family FPGAs
Word Width 9 9 9 9 9 9 Word Depth 256 256 88 blocks 256 256 256 9 256 256
9 9 256 256
Figure 1-23 * APA1000 Memory Block Architecture
Word Width 9 Word Depth 256 9 9 9 9
256 256
256 256 256 words x 18 bits, 1 read, 1 write
256
256 256
256
512 words x 18 bits, 1 read, 1 write
256 1,024 words x 9 bits, 1 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 23,040
Figure 1-24 * Example Showing Memory Arrays with Different Widths and Depths
Word Width 9 Word Depth 9 9
9 9 9
Write Port 9
9 9
Write Port
256 256 256 256
256 256 Read Ports 256 words x 9 bits, 2 read, 1 write
256 256 256 256 Read Ports 512 words x 9 bits, 4 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 6,912
Figure 1-25 * Multi-Port Memory Usage
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Design Environment
The ProASICPLUS family of FPGAs is fully supported by both Actel's Libero(R) Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see Actel's website for more information about Libero IDE). Libero IDE includes Synplify(R) AE from Synplicity(R), ViewDraw(R) AE from Mentor Graphics(R), ModelSim(R) HDL Simulator from Mentor Graphics, WaveFormer LiteTM AE from SynaptiCAD(R), PALACETM AE Physical Synthesis from Magma, and Designer software from Actel. PALACE is an effective tool when designing with ProASICPLUS. PALACE AE Physical Synthesis from Magma takes an EDIF netlist and optimizes the performance of ProASICPLUS devices through a physical placement-driven process, ensuring that timing closure is easily achieved. Actel's Designer software is a place-and-route tool that provides a comprehensive suite of back-end support tools for FPGA development. The Designer software includes the following: * Timer - a world-class integrated static timing analyzer and constraints editor that support timing-driven place-and-route NetlistViewer - a design netlist schematic viewer ChipPlanner - a graphical floorplanner viewer and editor SmartPower - allows the designer to quickly estimate the power consumption of a design PinEditor - a graphical application for editing pin assignments and I/O attributes I/O Attribute Editor - displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, Actel's back-annotation flow is compatible with all the major simulators. Another tool included in the Designer software is the SmartGen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems.
ISP
The user can generate *.bit or *.stp programming files from the Designer software and can use these files to program a device. ProASICPLUS devices can be programmed in-system. For more information on ISP of ProASICPLUS devices, refer to the In-System Programming ProASICPLUS Devices and Performing Internal In-System Programming Using Actel's ProASICPLUS Devices application notes. Prior to being programmed for the first time, the ProASICPLUS device I/Os are in a tristate condition with the pull-up resistor option enabled.
* * * * *
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Related Documents
Application Notes
Efficient Use of ProASIC Clock Trees http://www.actel.com/documents/A500K_Clocktree_AN.pdf I/O Features in ProASICPLUS Flash FPGAs http://www.actel.com/documents/APA_LVPECL_AN.pdf Power-Up Behavior of ProASICPLUS Devices http://www.actel.com/documents/APA_PowerUp_AN.pdf ProASICPLUS PLL Dynamic Reconfiguration Using JTAG http://www.actel.com/documents/APA_PLLdynamic_AN.pdf Using ProASICPLUS Clock Conditioning Circuits http://www.actel.com/documents/APA_PLL_AN.pdf In-System Programming ProASICPLUS Devices http://www.actel.com/documents/APA_External_ISP_AN.pdf Performing Internal In-System Programming Using Actel's ProASICPLUS Devices http://www.actel.com/documents/APA_Microprocessor_AN.pdf ProASICPLUS RAM and FIFO Blocks http://www.actel.com/documents/APA_RAM_FIFO_AN.pdf
White Paper
Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.actel.com/documents/DesignSecurity_WP.pdf
User's Guide
Designer User's Guide http://www.actel.com/documents/designer_UG.pdf SmartGen Cores Reference Guide http://www.actel.com/documents/gen_refguide_ug.pdf ProASIC and ProASICPLUS Macro Library Guide http://www.actel.com/documents/pa_libguide_UG.pdf
Additional Information
The following link contains additional information on ProASICPLUS devices. http://www.actel.com/products/proasicplus/default.aspx
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Package Thermal Characteristics
The ProASICPLUS family is available in several package types with a range of pin counts. Actel has selected packages based on high pin count, reliability factors, and superior thermal characteristics. Thermal resistance defines the ability of a package to conduct heat away from the silicon, through the package to the surrounding air. Junction-to-ambient thermal resistance is measured in degrees Celsius/Watt and is represented as Theta ja (ja). The lower the thermal resistance, the more efficiently a package will dissipate heat. A package's maximum allowed power (P) is a function of maximum junction temperature (TJ), maximum ambient operating temperature (TA), and junction-to-ambient thermal resistance ja. Maximum junction temperature is
the maximum allowable temperature on the active surface of the IC and is 110 C. P is defined as:
T J - TA P = -----------------ja
EQ 1-4 ja is a function of the rate (in linear feet per minute
(lfpm)) of airflow in contact with the package. When the estimated power consumption exceeds the maximum allowed power, other means of cooling, such as increasing the airflow rate, must be used. The maximum power dissipation allowed for a Military temperature device is specified as a function of jc. The absolute maximum junction temperature is 150C. The calculation of the absolute maximum power dissipation allowed for a Military temperature application is illustrated in the following example for a 456-pin PBGA package:
Max. junction temp. (C) - Max. case temp. (C) 150C - 125C Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------ = ------------------------------------- = 8.333W 3.0C/W jc (C/W) EQ 1-5 Table 1-15 * Package Thermal Characteristics
ja
Plastic Packages Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Plastic Quad Flat Pack (PQFP) PQFP with Heat spreader
2 1
Pin Count 100 144 208 208 456 144 256 484 484 676 896 1152 208 352 624
jc
14.0 11.0 8.0 3.8 3.0 3.8 3.8 3.2 3.2 3.2 2.4 1.8 2.0 2.0 6.5
Still Air 33.5 33.5 26.1 16.2 15.6 26.9 26.6 18.0 20.5 16.4 13.6 12.0 22.0 17.9 8.9
1.0 m/s 200 ft./min. 27.4 28.0 22.5 13.3 12.5 22.9 22.8 14.7 17.0 13.0 10.4 8.9 19.8 16.1 8.5
2.5 m/s 500 ft./min. 25.0 25.7 20.8 11.9 11.6 21.5 21.5 13.6 15.9 12.0 9.4 7.9 18.0 14.7 8.0
Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W
Plastic Ball Grid Array (PBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA)3 Fine Pitch Ball Grid Array (FBGA)4 Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) Ceramic Column Grid Array (CCGA/LGA) Notes: 1. 2. 3. 4.
Valid for the following devices irrespective of temperature grade: APA075, APA150, and APA300 Valid for the following devices irrespective of temperature grade: APA450, APA600, APA750, and APA1000 Depopulated Array Full array
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Calculating Typical Power Dissipation
ProASICPLUS device power is calculated with both a static and an active component. The active component is a function of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following formula:
Total Power Consumption--Ptotal
Ptotal = Pdc + Pac where: Pdc = 7 mW for the APA075 8 mW for the APA150 11 mW for the APA300 12 mW for the APA450 12 mW for the APA600 13 mW for the APA750 19 mW for the APA1000 Pdc includes the static components of PVDDP + PVDD + PAVDD Pac = Pclock + Pstorage + Plogic + Poutputs + Pinputs + Ppll + Pmemory
Global Clock Contribution--Pclock Pclock, the clock component of power dissipation, is given by the piece-wise model: for R < 15000 the model is: (P1 + (P2*R) - (P7*R2)) * Fs (lightly-loaded clock trees) for R > 15000 the model is: (P10 + P11*R) * Fs (heavily-loaded clock trees) where:
P1 P2 P7 P10 P11 R Fs = 100 W/MHz is the basic power consumption of the clock tree per MHz of the clock = 1.3 W/MHz is the incremental power consumption of the clock tree per storage tile - also per MHz of the
clock
= 0.00003 W/MHz is a correction factor for partially-loaded clock trees = 6850 W/MHz is the basic power consumption of the clock tree per MHz of the clock = 0.4 W/MHz is the incremental power consumption of the clock tree per storage tile - also per MHz of
the clock
= the number of storage tiles clocked by this clock = the clock frequency
Storage-Tile Contribution--Pstorage Pstorage, the storage-tile (Register) component of AC power dissipation, is given by
Pstorage = P5 * ms * Fs where: P5 ms Fs = = = 1.1 W/MHz is the average power consumption of a storage tile per MHz of its output toggling rate. The maximum output toggling rate is Fs/2. the number of storage tiles (Register) switching during each Fs cycle the clock frequency
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Logic-Tile Contribution--Plogic Plogic, the logic-tile component of AC power dissipation, is given by
Plogic = P3 * mc * Fs where: P3 mc Fs = = = 1.4 W/MHz is the average power consumption of a logic tile per MHz of its output toggling rate. The maximum output toggling rate is Fs/2. the number of logic tiles switching during each Fs cycle the clock frequency
I/O Output Buffer Contribution--Poutputs Poutputs, the I/O component of AC power dissipation, is given by
Poutputs = (P4 + (Cload * VDDP2)) * p * Fp where: P4 = 326 W/MHz is the intrinsic power consumption of an output pad normalized per MHz of the output frequency. This is the total I/O current VDDP. the output load the number of outputs the average output frequency
Cload = p = Fp =
I/O Input Buffer's Buffer Contribution--Pinputs The input's component of AC power dissipation is given by
Pinputs = P8 * q * Fq where: P8 q Fq = = = 29 W/MHz is the intrinsic power consumption of an input pad normalized per MHz of the input frequency. the number of inputs the average input frequency
PLL Contribution--Ppll
Ppll = P9 * Npll where: P9 NPll = = 7.5 mW. This value has been estimated at maximum PLL clock frequency. number of PLLs used
RAM Contribution--Pmemory Finally, Pmemory, the memory component of AC power consumption, is given by
Pmemory = P6 * Nmemory * Fmemory * Ememory where: P6 Nmemory Fmemory Ememory = = = = 175 W/MHz is the average power consumption of a memory block per MHz of the clock the number of RAM/FIFO blocks (1 block = 256 words * 9 bits) the clock frequency of the memory the average number of active blocks divided by the total number of blocks (N) of the memory. * * Typical values for Ememory would be 1/4 for a 1k x 8,9,16, 32 memory and 1/16 for a 4kx8, 9, 16, and 32 memory configuration In addition, an application-dependent component to Ememory can be considered. For example, for a 1kx8 memory configuration using only 1 cycle out of 2, Ememory = 1/4*1/2 = 1/8
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The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as follows:
Pclock
Fs R => = 10 MHz = 13,440
Pclock = (P1 + (P2*R) - (P7*R2)) * Fs = 121.5 mW ms = 13,440 (in a shift register 100% of storage tiles are toggling at each clock cycle and Fs = 10 MHz)
Pstorage
=> Pstorage = P5 * ms * Fs = 147.8 mW mc => = 0 (no logic tiles in this shift register)
Plogic
Plogic = 0 mW Cload VDDP p Fp => = = = = 40 pF 3.3 V 24 5 MHz
Poutputs
Poutputs = (P4 + (Cload * VDDP2)) * p * Fp = 91.4 mW q Fq = = 1 10 MHz
Pinputs
=>
Pinputs = P8 * q * Fq = 0.3 mW Nmemory = 0 (no RAM/FIFO blocks in this shift register)
Pmemory
=> Pac => 361 mW Ptotal Pdc + Pac = 374 mW (typical) Pmemory = 0 mW
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Operating Conditions
Standard and -F parts are the same unless otherwise noted. All -F parts are only available as commercial.
Table 1-16 * Absolute Maximum Ratings* Parameter Supply Voltage Core (VDD) Supply Voltage I/O Ring (VDDP) DC Input Voltage PCI DC Input Voltage PCI DC Input Clamp Current (absolute) LVPECL Input Voltage GND VIN < -1 or VIN = VDDP + 1 V Condition Minimum -0.3 -0.3 -0.3 -1.0 10 -0.3 0 VDDP + 0.5 0 Maximum 3.0 4.0 VDDP + 0.3 VDDP + 1.0 Units V V V V mA V V
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 1-17 * Programming, Storage, and Operating Limits Storage Temperature Operating TJ Max. Junction Temperature 110C 110C 150C 150C
Product Grade Commercial Industrial Military MIL-STD-883
Programming Cycles (min.) 500 500 100 100
Program Retention (min.) 20 years 20 years Refer to Table 1-18 on page 1-34 Refer to Table 1-18 on page 1-34
Min. -55C -55C -65C -65C
Max. 110C 110C 150C 150C
Performance Retention
For devices operated and stored at 110C or less, the performance retention period is 20 years after programming. For devices operated and stored at temperatures greater than 110C, refer to Table 1-18 on page 1-34 to determine the performance retention period. Actel does not guarantee performance if the performance retention period is exceeded. Designers can determine the performance retention period from the following table. Evaluate the percentage of time spent at the highest temperature, then determine the next highest temperature to which the device will be exposed. In Table 1-18 on page 1-34, find the temperature profile that most closely matches the application.
Example - the ambient temperature of a system cycles between 100C (25% of the time) and 50C (75% of the time). No forced ventilation cooling system is in use. An APA600-PQ208M FPGA operates in the system, dissipating 1 W. The package thermal resistance (junction-to-ambient) in still air ja is 20C/W, indicating that the junction temperature of the FPGA will be 120C (25% of the time) and 70C (75% of the time). The entry in Table 1-18 on page 1-34, which most closely matches the application, is 25% at 125C with 75% at 110C. Performance retention in this example is at least 16.0 years. Note that exceeding the stated retention period may result in a performance degradation in the FPGA below the worst-case performance indicated in the Actel Timer. To ensure that performance does not degrade below the worst-case values in the Actel Timer, the FPGA must be reprogrammed within the performance retention period. In addition, note that performance retention is independent of whether or not the FPGA is operating. The retention period of a device in storage at a given temperature will be the same as the retention period of a device operating at that junction temperature.
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Table 1-18 * Military Temperature Grade Product Performance Retention Minimum Time at TJ 110C or below 100% 90% 75% 90% 50% 90% 75% 100% 90% 50% 75% 90% 75% 50% 75% 100% 90% 50% 50% 75% 50% 10% 50% 50% 25% 50% 100% 50% 25% 10% 50% 25% 10% 25% 25% 50% 10% 10% 25% 10% Minimum Time at TJ 125C or below Minimum Time at TJ 135C or below Minimum Time at TJ 150C or below Minimum Performance Retention (Years) 20.0 18.2 16 15.4 13.3 11.8 11.4 10 9.1 8 8 7.7 7.3 6.7 5.7 5 4.5 4.4 4 4 3.3 2.5
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Table 1-19 * Recommended Maximum Operating Conditions Programming and PLL Supplies Commercial/Industrial/Military/MIL-STD-883 Parameter VPP VPN IPP IPN AVDD AGND Condition During Programming Normal Operation Normal Operation
1
Minimum 15.8 0 -13.8 -13.8
Maximum 16.5 16.5 -13.2 0.5 25 10
Units V V V V mA mA V V
During Programming
2
During Programming During Programming VDD GND
VDD GND
Notes: 1. Please refer to the "VPP Programming Supply Pin" section on page 1-74 for more information. 2. Please refer to the "VPN Programming Supply Pin" section on page 1-74 for more information. Table 1-20 * Recommended Operating Conditions Limits Parameter DC Supply Voltage (2.5 V I/Os) DC Supply Voltage (3.3 V I/Os) Operating Ambient Temperature Range Maximum Operating Junction Temperature Symbol VDD and VDDP VDDP VDD TA, TC TJ Commercial 2.5 V 0.2 V 3.3 V 0.3 V 2.5 V 0.2 V 0C to 70C 110C Industrial 2.5 V 0.2 V 3.3 V 0.3 V 2.5 V 0.2 V -40C to 85C 110C Military/MIL-STD-883 2.5 V 0.2 V 3.3 V 0.3 V 2.5 V 0.2 V -55C (TA) to 125C (TC) 150C
Note: For I/O long-term reliability, external pull-up resistors cannot be used to increase output voltage above VDDP.
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Table 1-21 * DC Electrical Specifications (VDDP = 2.5 V 0.2V) Commercial/Industrial/ Military/MIL-STD-8831, 2 Symbol VOH Parameter Output High Voltage High Drive (OB25LPH) IOH = -6 mA IOH = -12 mA IOH = -24 mA IOH = -3 mA IOH = -6 mA IOH = -8 mA IOL = 8 mA IOL = 15 mA IOL = 24 mA IOL = 4 mA IOL = 8 mA IOL = 15 mA 1.7 -0.3 VIN 1.25 V See Table 1-4 on page 1-9 with pull up (VIN = GND) without pull up (VIN = GND or VDD) IDDQ Quiescent Supply Current (standby) Commercial Quiescent Supply Current (standby) Industrial Quiescent Supply Current (standby) Military/MIL-STD-883 VIN = GND4 or VDD Std. -F3 VIN = GND4 or VDD Std. 5.0 VIN = GND4 or VDD Std. 5.0 Std. -F3, 5 Notes: 1. 2. 3. 4. 5. 6. 7. All process conditions. Commercial/Industrial: Junction Temperature: -40 to +110C. All process conditions. Military: Junction Temperature: -55 to +150C. All -F parts are available only as commercial. No pull-up resistor. This will not exceed 2 mA total per device. During transitions, the input signal may overshoot to VDDP +1.0V for a limited time of no larger than 10% of the duty cycle. During transitions, the input signal may undershoot to -1.0V for a limited time of no larger than 10% of the duty cycle. -10 -10 25 10 100 mA A A 20 mA 6 0.3 -240 -10 5.0 5.0 0.35 2.1 2.0 1.7 2.1 1.9 1.7 0.2 0.4 0.7 0.2 0.4 0.7 VDDP + 0.3 0.7 56 0.45 - 20 10 15 25 V V k V A A mA mA Conditions Min. Typ. Max. Units
V
Low Drive (OB25LPL)
VOL
Output Low Voltage High Drive (OB25LPH)
V
Low Drive (OB25LPL)
VIH6 VIL7
Input High Voltage Input Low Voltage
RWEAKPULLUP Weak Pull-up Resistance (OTB25LPU) HYST IIN Input Hysteresis Schmitt Input Current
IDDQ
IDDQ
IOZ
Tristate Output Leakage Current VOH = GND or VDD
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Table 1-21 * DC Electrical Specifications (VDDP = 2.5 V 0.2V) (Continued) Commercial/Industrial/ Military/MIL-STD-8831, 2 Symbol IOSH Parameter Conditions Min. -120 -100 mA 100 30 10 10 pF pF Typ. Max. Units mA
Output Short Circuit Current High High Drive (OB25LPH) VIN = VSS VIN = VSS Low Drive (OB25LPL) Output Short Circuit Current Low High Drive (OB25LPH) VIN = VDDP VIN = VDDP Low Drive (OB25LPL) I/O Pad Capacitance Clock Input Pad Capacitance
IOSL
CI/O CCLK Notes: 1. 2. 3. 4. 5. 6. 7.
All process conditions. Commercial/Industrial: Junction Temperature: -40 to +110C. All process conditions. Military: Junction Temperature: -55 to +150C. All -F parts are available only as commercial. No pull-up resistor. This will not exceed 2 mA total per device. During transitions, the input signal may overshoot to VDDP +1.0V for a limited time of no larger than 10% of the duty cycle. During transitions, the input signal may undershoot to -1.0V for a limited time of no larger than 10% of the duty cycle.
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Table 1-22 * DC Electrical Specifications (VDDP = 3.3 V 0.3 V and VDD = 2.5 V 0.2 V) Commercial/Industrial/ Military/MIL-STD-8831, 2 Symbol VOH Parameter Output High Voltage 3.3 V I/O, High Drive (OB33P) Conditions IOH = -14 mA IOH = -24 mA IOH = -6 mA IOH = -12 mA IOL = 15 mA IOL = 20 mA IOL = 28 mA IOL = 7 mA IOL = 10 mA IOL = 15 mA VIH6 Input High Voltage 3.3 V Schmitt Trigger Inputs 3.3 V LVTTL/LVCMOS 2.5 V Mode Input Low Voltage 3.3 V Schmitt Trigger Inputs 3.3 V LVTTL/LVCMOS 2.5 V Mode Resistance VIN 1.5 V Resistance VIN 1.5 V with pull up (VIN = GND) without pull up (VIN = GND or VDD) IDDQ Quiescent Supply Current (standby) Commercial Quiescent Supply Current (standby) Industrial Quiescent Supply Current (standby) Military VIN = GND4 or VDD Std. -F3 VIN = GND4 or VDD Std. VIN = GND4 or VDD Std. 5.0 25 mA 5.0 20 mA 1.6 2 1.7 -0.3 -0.3 -0.3 7 7 -300 -10 5.0 5.0 Min. 0.9VDDP 2.4 0.9VDDP 2.4 0.1VDDP 0.4 0.7 0.1VDDP 0.4 0.7 VDDP + 0.3 VDDP + 0.3 VDDP + 0.3 0.8 0.8 0.7 43 43 -40 10 15 25 Typ. Max. Units
V
3.3 V I/O, Low Drive (OB33L) VOL Output Low Voltage 3.3 V I/O, High Drive (OB33P)
3.3 V I/O, Low Drive (OB33L)
V
V
VIL7
V k k A A mA mA
Pull-up RWEAKPULLUP Weak (IOB33U) RWEAKPULLUP Weak Pull-up (IOB25U) IIN Input Current
IDDQ
IDDQ
Notes: 1. 2. 3. 4. 5. 6. 7. All process conditions. Commercial/Industrial: Junction Temperature: -40 to +110C. All process conditions. Military: Junction Temperature: -55 to +150C. All -F parts are only available as commercial. No pull-up resistor required. This will not exceed 2 mA total per device. During transitions, the input signal may overshoot to VDDP +1.0 V for a limited time of no larger than 10% of the duty cycle. During transitions, the input signal may undershoot to -1.0 V for a limited time of no larger than 10% of the duty cycle.
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Table 1-22 * DC Electrical Specifications (VDDP = 3.3 V 0.3 V and VDD = 2.5 V 0.2 V) (Continued) Commercial/Industrial/ Military/MIL-STD-8831, 2 Symbol IOZ Parameter Tristate Current Output Conditions Leakage VOH = GND or VDD Std. -F3, 5 Min. -10 -10 Typ. Max. 10 100 Units A A
IOSH
Output Short Circuit Current High 3.3 V High Drive (OB33P) VIN = GND 3.3 V Low Drive (OB33L) VIN = GND Output Short Circuit Current Low 3.3 V High Drive VIN = VDD VIN = VDD 3.3 V Low Drive I/O Pad Capacitance Clock Input Pad Capacitance
-200 -100
IOSL
200 100 10 10 pF pF
CI/O CCLK Notes: 1. 2. 3. 4. 5. 6. 7.
All process conditions. Commercial/Industrial: Junction Temperature: -40 to +110C. All process conditions. Military: Junction Temperature: -55 to +150C. All -F parts are only available as commercial. No pull-up resistor required. This will not exceed 2 mA total per device. During transitions, the input signal may overshoot to VDDP +1.0 V for a limited time of no larger than 10% of the duty cycle. During transitions, the input signal may undershoot to -1.0 V for a limited time of no larger than 10% of the duty cycle.
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Table 1-23 * DC Specifications (3.3 V PCI Operation)1 Commercial/ Industrial2,3 Symbol VDD VDDP VIH VIL IIPU IIL Parameter Supply Voltage for Core Supply Voltage for I/O Ring Input High Voltage Input Low Voltage Input Pull-up Voltage
4
Military/MIL-STD- 8832,3 Min. 2.3 3.0 0.5VDDP -0.5 0.7VDDP Max. 2.7 3.6 VDDP + 0.5 0.3VDDP Units V V V V V 50 A A 0.9VDDP V 0.1VDDP 10 5 12 V pF pF
Condition
Min. 2.3 3.0
Max. 2.7 3.6
0.5VDDP VDDP + 0.5 -0.5 0.7VDDP 0 < VIN < VDDP Std. -F
3, 6
0.3VDDP
Input Leakage Current5
-10 -10 0.9VDDP
10 100
-50
VOH VOL CIN CCLK Notes: 1. 2. 3. 4.
Output High Voltage Output Low Voltage Input Pin Capacitance (except CLK) CLK Pin Capacitance
IOUT = -500 A IOUT = 1500 A
0.1VDDP 10 5 12
For PCI operation, use GL33, OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only. All process conditions. Junction Temperature: -40 to +110C for Commercial and Industrial devices and -55 to +125C for Military. All -F parts are available as commercial only. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum current at this input voltage. 5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 6. The sum of the leakage currents for all inputs shall not exceed 2mA per device.
1 -4 0
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ProASICPLUS Flash Family FPGAs
Table 1-24 * AC Specifications (3.3 V PCI Revision 2.2 Operation) Commercial/Industrial/Military/MIL-STD- 883 Symbol Parameter IOH(AC) Switching Current High Condition 0 < VOUT 0.3VDDP* 0.3VDDP VOUT < 0.7VDDP < VOUT < 0.9VDDP* VDDP* Min. -12VDDP (-17.1 + (VDDP - VOUT)) See equation C - page 124 of the PCI Specification document rev. 2.2 -32VDDP 16VDDP
1
Max.
Units mA mA
(Test Point) IOL(AC) Switching Current Low
VOUT = 0.7VDDP* VDDP > VOUT 0.6VDDP*
mA mA mA
0.6VDDP > VOUT > 0.1VDDP 0.18VDDP > VOUT > 0*
(26.7VOUT) See equation D - page 124 of the PCI Specification document rev. 2.2 38VDDP -25 + (VIN + 1)/0.015 25 + (VIN - VDDP - 1)/0.015 1 1 4 4
(Test Point) ICL ICH slewR slewF Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate
VOUT = 0.18VDDP -3 < VIN -1 VDDP + 4 > VIN VDDP + 1 0.2VDDP to 0.6VDDP 0.6VDDP to 0.2VDDP load* load*
mA mA mA V/ns V/ns
Note: * Refer to the PCI Specification document rev. 2.2.
Pad Loading Applicable to the Rising Edge PCI
pin 1/2 in. max output buffer 1k 10 pF
Pad Loading Applicable to the Falling Edge PCI
pin output buffer
1k 10 pF
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1-41
ProASICPLUS Flash Family FPGAs
Tristate Buffer Delays
EN A OTBx A PAD VOL tDLH 50% 50% VOH 50% tDHL 50% 50% 50% VDDP 50% PAD VOL tENZL EN
PAD 35pF EN 10% PAD GND tENZH 50% 50% VOH 50%
90%
Figure 1-26 * Tristate Buffer Delays Table 1-25 * Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 70C Max tDLH1 Macro Type OTB33PH OTB33PN OTB33PL OTB33LH OTB33LN OTB33LL Notes: 1. 2. 3. 4. 5. tDLH=Data-to-Pad High tDHL=Data-to-Pad Low tENZH=Enable-to-Pad, Z to High tENZL = Enable-to-Pad, Z to Low All -F parts are only available as commercial. Description 3.3 V, PCI Output Current, High Slew Rate 3.3 V, High Output Current, Nominal Slew Rate 3.3 V, High Output Current, Low Slew Rate 3.3 V, Low Output Current, High Slew Rate 3.3 V, Low Output Current, Nominal Slew Rate 3.3 V, Low Output Current, Low Slew Rate Std. 2.0 2.2 2.5 2.6 2.9 3.0 -F 2.4 2.6 3.0 3.1 3.5 3.6 Max tDHL2 Std. 2.2 2.9 3.2 4.0 4.3 5.6 -F 2.6 3.5 3.9 4.8 5.2 6.7 Max tENZH3 Std. 2.2 2.4 2.7 2.8 3.2 3.3 2.6 2.9 3.3 3.4 3.8 3.9 Max tENZL4 -F 2.4 2.5 3.4 3.6 4.9 6.6 Units ns ns ns ns ns ns 2.0 2.1 2.8 3.0 4.1 5.5
-F Std.
Table 1-26 * Worst-Case Commercial Conditions VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 70C Max tDLH1 Macro Type OTB25LPHH OTB25LPHN OTB25LPHL OTB25LPLH OTB25LPLN OTB25LPLL Notes: 1. 2. 3. 4. 5. 6.
1 -4 2
Max tDHL2 Std. 2.1 3.0 3.2 4.6 4.2 5.3 -F 2.5 3.6 3.8 5.5 5.1 6.4
Max tENZH3 Std. 2.3 2.7 3.1 3.0 3.8 4.2 2.7 3.2 3.8 3.6 4.5 5.1
Max tENZL4 -F 2.4 2.5 3.2 3.1 4.6 6.1 Units ns ns ns ns ns ns 2.0 2.1 2.7 2.6 3.8 5.1
Description 2.5 V, Low Power, High Output Current, High Slew Rate5 2.5 V, Low Power, High Output Current, Nominal Slew Rate 2.5 V, Low Power, High Output Current, Low Slew Rate5 Rate5 2.5 V, Low Power, Low Output Current, High Slew Rate5 2.5 V, Low Power, Low Output Current, Nominal Slew 2.5 V, Low Power, Low Output Current, Low Slew Rate5
5
Std. 2.0 2.4 2.9 2.7 3.5 4.0
-F 2.4 2.9 3.5 3.3 4.2 4.8
-F Std.
tDLH=Data-to-Pad High tDHL=Data-to-Pad Low tENZH=Enable-to-Pad, Z to High tENZL = Enable-to-Pad, Z to Low Low power I/O work with VDDP=2.5 V 10% only. VDDP=2.3 V for delays. All -F parts are only available as commercial.
v5.7
ProASICPLUS Flash Family FPGAs
Table 1-27 * Worst-Case Military Conditions VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 125C for Military/MIL-STD-883 Max tDLH1 Macro Type OTB33PH OTB33PN OTB33PL OTB33LH OTB33LN OTB33LL Notes: 1. 2. 3. 4. tDLH=Data-to-Pad High tDHL=Data-to-Pad Low tENZH=Enable-to-Pad, Z to High tENZL = Enable-to-Pad, Z to Low Description 3.3 V, PCI Output Current, High Slew Rate 3.3 V, High Output Current, Nominal Slew Rate 3.3 V, High Output Current, Low Slew Rate 3.3 V, Low Output Current, High Slew Rate 3.3 V, Low Output Current, Nominal Slew Rate 3.3 V, Low Output Current, Low Slew Rate Std. 2.2 2.4 2.7 2.7 3.3 3.2 Max tDHL2 Std. 2.4 3.2 3.5 4.3 4.7 6.0 Max tENZH3 Std. 2.3 2.7 2.9 3.0 3.4 3.5 Max tENZL4 Std. 2.1 2.3 3.0 3.1 4.4 5.9 Units ns ns ns ns ns ns
Table 1-28 * Worst-Case Military Conditions VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 125C for Military/MIL-STD-883 Max tDLH1 Macro Type OTB25LPHH OTB25LPHN OTB25LPHL OTB25LPLH OTB25LPLN OTB25LPLL Notes: 1. 2. 3. 4. 5. tDLH=Data-to-Pad High tDHL=Data-to-Pad Low tENZH=Enable-to-Pad, Z to High tENZL = Enable-to-Pad, Z to Low Low power I/O work with VDDP=2.5V 10% only. VDDP=2.3V for delays. Description 2.5 V, Low Power, High Output Current, High Slew Rate
5
Max tDHL2 Std. 2.3 3.2 3.5 5.0 4.5 5.8
Max tENZH3 Std. 2.4 2.8 3.3 3.2 4.1 4.4
Max tENZL4 Std. 2.1 2.1 2.8 2.8 4.1 5.4 Units ns ns ns ns ns ns
Std. 2.3 2.7 3.2 3.0
5
2.5 V, Low Power, High Output Current, Nominal Slew Rate5 2.5 V, Low Power, High Output Current, Low Slew Rate5 2.5 V, Low Power, Low Output Current, High Slew Rate5
2.5 V, Low Power, Low Output Current, Nominal Slew Rate 2.5 V, Low Power, Low Output Current, Low Slew Rate
5
3.7 4.4
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1-43
ProASICPLUS Flash Family FPGAs
Output Buffer Delays
A A OBx PAD 35pF 50% 50% VOH 50% PAD 50% VOL tDLH tDHL
Figure 1-27 * Output Buffer Delays Table 1-29 * Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 70C Max tDLH1 Macro Type OB33PH OB33PN OB33PL OB33LH OB33LN OB33LL Notes: 1. tDLH = Data-to-Pad High 2. tDHL = Data-to-Pad Low 3. All -F parts are only available as commercial. Table 1-30 * Worst-Case Commercial Conditions VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 70C Max tDLH1 Macro Type OB25LPHH OB25LPHN OB25LPHL OB25LPLH OB25LPLN OB25LPLL Notes: 1. 2. 3. 4. tDLH = Data-to-Pad High tDHL = Data-to-Pad Low Low-power I/Os work with VDDP=2.5 V 10% only. VDDP=2.3 V for delays. All -F parts are only available as commercial. Description 2.5 V, Low Power, High Output Current, High Slew Rate3 Std. 2.0 2.4 2.9 2.7
3
Max tDHL2 Std. 2.2 2.9 3.2 4.0 4.3 5.6 -F 2.6 3.5 3.9 4.8 5.2 6.7 Units ns ns ns ns ns ns
Description 3.3 V, PCI Output Current, High Slew Rate 3.3 V, High Output Current, Nominal Slew Rate 3.3 V, High Output Current, Low Slew Rate 3.3 V, Low Output Current, High Slew Rate 3.3 V, Low Output Current, Nominal Slew Rate 3.3 V, Low Output Current, Low Slew Rate
Std. 2.0 2.2 2.5 2.6 2.9 3.0
-F 2.4 2.6 3.0 3.1 3.5 3.6
Max tDHL2 Std. 2.1 3.0 3.2 4.6 4.2 5.3 -F 2.6 3.6 3.8 5.5 5.1 6.4 Units ns ns ns ns ns ns
-F 2.4 2.9 3.5 3.3 4.2 4.8
2.5 V, Low Power, High Output Current, Nominal Slew Rate3 2.5 V, Low Power, High Output Current, Low Slew Rate 2.5 V, Low Power, Low Output Current, High Slew
3
Rate3
2.5 V, Low Power, Low Output Current, Nominal Slew Rate 2.5 V, Low Power, Low Output Current, Low Slew Rate3
3.5 4.0
1 -4 4
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ProASICPLUS Flash Family FPGAs
Table 1-31 * Worst-Case Military Conditions VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 125C for Military/MIL-STD-883 Max. tDLH1 Macro Type OB33PH OB33PN OB33PL OB33LH OB33LN OB33LL Notes: 1. tDLH = Data-to-Pad High 2. tDHL = Data-to-Pad Low Table 1-32 * Worst-Case Military Conditions VDDP = 2.3 V, VDD = 2.3V, 35 pF load, TJ = 125C for Military/MIL-STD-883 Max. tDLH1 Macro Type OB25LPHH OB25LPHN OB25LPHL OB25LPLH OB25LPLN OB25LPLL Notes: 1. tDLH = Data-to-Pad High 2. tDHL = Data-to-Pad Low 3. Low power I/O work with VDDP=2.5V 10% only. VDDP=2.3V for delays. Description 2.5V, Low Power, High Output Current, High Slew Rate
3 3
Max. tDHL2 Std. 2.3 3.2 3.5 4.3 4.7 6.1 Units ns ns ns ns ns ns
Description 3.3V, PCI Output Current, High Slew Rate 3.3V, High Output Current, Nominal Slew Rate 3.3V, High Output Current, Low Slew Rate 3.3V, Low Output Current, High Slew Rate 3.3V, Low Output Current, Nominal Slew Rate 3.3V, Low Output Current, Low Slew Rate
Std. 2.1 2.5 2.7 2.7 3.3 3.3
Max. tDHL2 Std. 2.4 3.3 3.5 5.0 4.6 5.7 Units ns ns ns ns ns ns
Std. 2.3 2.7 3.2 3.0
3
2.5V, Low Power, High Output Current, Nominal Slew Rate 2.5V, Low Power, High Output Current, Low Slew Rate3
2.5V, Low Power, Low Output Current, High Slew Rate3 2.5V, Low Power, Low Output Current, Nominal Slew Rate 2.5V, Low Power, Low Output Current, Low Slew Rate3
3.9 4.3
v5.7
1-45
ProASICPLUS Flash Family FPGAs
Input Buffer Delays
V DDP PAD PAD IBx Y Y GND 50% 50% VDD 50% tINYH 0V 50% tIN YL
Figure 1-28 * Input Buffer Delays Table 1-33 * Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, TJ = 70C Max. tINYH1 Macro Type IB33 IB33S Notes: 1. 2. 3. 4. 5. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3 V for delays. All -F parts are only available as commercial. 3.3 V, CMOS Input Levels3, Description No Pull-up Resistor Std. 0.4 0.6 -F 0.5 0.7 Max. tINYL2 Std. 0.6 0.8 -F 0.7 0.9 Units ns ns
3.3 V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger
Table 1-34 * Worst-Case Commercial Conditions VDDP = 2.3 V, VDD = 2.3 V, TJ = 70C Max. tINYH1 Macro Type IB25LP IB25LPS Notes: 1. 2. 3. 4. 5. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3 V for delays. All -F parts are only available as commercial. 2.5 V, CMOS Input Levels3,
3,
Max. tINYL2 Std. 0.6 0.9 -F 0.8 1.1 Units ns ns
Description Low Power
Std. 0.9 0.7
-F 1.1 0.9
2.5 V, CMOS Input Levels Low Power, Schmitt Trigger
1 -4 6
v5.7
ProASICPLUS Flash Family FPGAs
Table 1-35 * Worst-Case Military Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 125C for Military/MIL-STD-883 Max. tINYH1 Macro Type IB33 IB33S Notes: 1. 2. 3. 4. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3V for delays. Description 3.3V, CMOS Input Levels3 , No Pull-up Resistor Std. 0.5 0.6 Max. tINYL2 Std. 0.6 0.8 Units ns ns
3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger
Table 1-36 * Worst-Case Military Conditions VDDP = 2.3V, VDD = 2.3V, TJ = 125C for Military/MIL-STD-883 Max. tINYH1 Macro Type IB25LP IB25LPS Notes: 1. 2. 3. 4. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3V for delays. Description 2.5V, CMOS Input Levels Low Power 2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger
3,
Max. tINYL2 Std. 0.7 1.0 Units ns ns
Std. 0.9 0.8
v5.7
1-47
ProASICPLUS Flash Family FPGAs
Global Input Buffer Delays
Table 1-37 * Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, TJ = 70C Max. tINYH1 Macro Type GL33 GL33S PECL Notes: 1. 2. 3. 4. 5. 6. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low Applies to Military ProASICPLUS devices. LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3 V for delays. All -F parts are only available as commercial.
4
Max. tINYL2 Std. 1.1 1.1 1.1
3
Units ns ns ns
Description 3.3 V, CMOS Input Levels4, No Pull-up Resistor 3.3 V, CMOS Input Levels , No Pull-up Resistor, Schmitt Trigger PPECL Input Levels
Std. 1.0 1.0 1.0
3
-F 1.2 1.2 1.2
-F 1.3 1.3 1.3
Table 1-38 * Worst-Case Commercial Conditions VDDP = 2.3 V, VDD = 2.3 V, TJ = 70C Max. tINYH1 Macro Type GL25LP GL25LPS Notes: 1. 2. 3. 4. 5. 6. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low Applies to Military ProASICPLUS devices. LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3 V for delays. All -F parts are only available as commercial.
4,
Max. tINYL2 Std.3 1.0 1.0 -F 1.3 1.1
Units ns ns
Description 2.5 V, CMOS Input Levels Low Power 2.5 V, CMOS Input Levels4, Low Power, Schmitt Trigger
Std. 1.1 1.3
3
-F 1.2 1.6
1 -4 8
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ProASICPLUS Flash Family FPGAs
Table 1-39 * Worst-Case Military Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 125C for Military/MIL-STD-883 Max. tINYH1 Macro Type GL33 GL33S PECL Notes: 1. 2. 3. 4. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3V for delays.
3
Max. tINYL2 Std. 1.1 1.1 1.1
Description 3.3V, CMOS Input Levels , No Pull-up Resistor 3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger PPECL Input Levels
Std. 1.1 1.1 1.1
Table 1-40 * Worst-Case Military Conditions VDDP = 2.3V, VDD = 2.3V, TJ = 125C for Military/MIL-STD-883 Max. tINYH1 Macro Type GL25LP GL25LPS Notes: 1. 2. 3. 4. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3V for delays. 2.5V, CMOS Input Levels3,
3,
Max. tINYL2 Std. 1.1 1.0
Description Low Power
Std. 1.0 1.4
2.5V, CMOS Input Levels Low Power, Schmitt Trigger
v5.7
1-49
ProASICPLUS Flash Family FPGAs
Predicted Global Routing Delay
Table 1-41 * Worst-Case Commercial Conditions1 VDDP = 3.0 V, VDD = 2.3 V, TJ = 70C Max. Parameter tRCKH tRCKL tRCKH tRCKL Notes: 1. 2. 3. 4. The timing delay difference between tile locations is less than 15ps. All -F parts are only available as commercial. Highly loaded row 50%. Minimally loaded row. Input Low to High Input High to Low Input Low to High Input High to Low
3 3 4 4
Description
Std. 1.1 1.0 0.8 0.8
-F2 1.3 1.2 1.0 1.0
Units ns ns ns ns
Table 1-42 * Worst-Case Military Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 125C for Military/MIL-STD-883 Parameter tRCKH tRCKL tRCKH tRCKL Description Input Low to High (high loaded row of 50%) Input High to Low (high loaded row of 50%) Input Low to High (minimally loaded row) Input High to Low (minimally loaded row) Max. 1.1 1.0 0.8 0.8 Units ns ns ns ns
Note: * The timing delay difference between tile locations is less than 15 ps.
Global Routing Skew
Table 1-43 * Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, TJ = 70C Max. Parameter tRCKSWH tRCKSHH Description Maximum Skew Low to High Maximum Skew High to Low Std. 270 270 -F* 320 320 Units ps ps
Note: *All -F parts are only available as commercial. Table 1-44 * Worst-Case Commercial Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 125C for Military/MIL-STD-883 Parameter tRCKSWH tRCKSHH Description Maximum Skew Low to High Maximum Skew High to Low Max. 270 270 Units ps ps
1 -5 0
v5.7
ProASICPLUS Flash Family FPGAs
Module Delays
A B C Y
A B C Y
50%50% 50% 50% 50%50% 50% 50% 50% 50% 50% 50%
tDBLH tDALH tDAHL tDBHL
tDCLH
tDCHL
Figure 1-29 * Module Delays
Sample Macrocell Library Listing
Table 1-45 * Worst-Case Military Conditions1 VDD = 2.3 V, TJ = 70 C, TJ = 70C, TJ = 125C for Military/MIL-STD-883 Std. Cell Name NAND2 AND2 NOR3 MUX2L OA21 XOR2 LDL 2-Input NAND 2-Input AND 3-Input NOR 2-1 MUX with Active Low Select 2-Input OR into a 2-Input AND 2-Input Exclusive OR Active Low Latch (LH/HL) CLK-Q tsetup thold DFFL Negative Edge-Triggered D-type Flip-Flop (LH/HL) CLK-Q tsetup thold Notes: 1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of local interconnect. 2. All -F parts are only available as commercial. 3. LH and HL refer to the Q transitions from Low to High and High to Low, respectively. LH3 HL3 0.9 0.8 0.6 0.0 LH3 HL3 Description Max 0.5 0.7 0.8 0.5 0.8 0.6 0.9 0.8 0.7 0.1 1.1 1.0 0.7 0.0 ns ns ns Min Max 0.6 0.8 1.0 0.6 1.0 0.8 1.1 0.9 0.8 0.2 ns ns ns ns -F2 Min Units ns ns ns ns ns ns ns
v5.7
1-51
ProASICPLUS Flash Family FPGAs
Table 1-46 * Recommended Operating Conditions Limits Parameter Maximum Clock Frequency* Maximum RAM Frequency* Maximum Rise/Fall Time on Inputs* * * Schmitt Trigger Mode (10% to 90%) Non-Schmitt Trigger Mode (10% to 90%) tR/tF tR/tF N/A 100 ns 180 MHz fTCK 10 MHz 100 ns 10 ns 180 MHz 10 MHz Symbol fCLOCK fRAM Commercial/Industrial 180 MHz 150 MHz Military/MIL-STD-883 180 MHz 150 MHz
Maximum LVPECL Frequency* Maximum TCK Frequency (JTAG)
Note: *All -F parts will be 20% slower than standard commercial devices. Table 1-47 * Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25C Type OB33PH OB33PN OB33PL OB33LH OB33LN OB33LL OB25LPHH OB25LPHN OB25LPHL OB25LPLH OB25LPLN OB25LPLL Notes: 1. Standard and -F parts. 2. All -F only available as commercial. Trig. Level Rising Edge (ns) 10%-90% 10%-90% 10%-90% 10%-90% 10%-90% 10%-90% 10%-90% 10%-90% 10%-90% 10%-90% 10%-90% 10%-90% 1.60 1.57 1.57 3.80 4.19 5.49 1.55 1.70 1.97 3.57 4.65 5.52 Slew Rate (V/ns) 1.65 1.68 1.68 0.70 0.63 0.48 1.29 1.18 1.02 0.56 0.43 0.36 Falling Edge (ns) 1.65 3.32 1.99 4.84 3.37 2.98 1.56 2.08 2.09 3.93 3.28 3.44 Slew Rate (V/ns) 1.60 0.80 1.32 0.55 0.78 0.89 1.28 0.96 0.96 0.51 0.61 0.58 PCI Mode Yes No No No No No No No No No No No
1 -5 2
v5.7
ProASICPLUS Flash Family FPGAs
Table 1-48 * JTAG Switching Characteristics Description Output delay from TCK falling to TDI, TMS TDO Setup time before TCK rising TDO Hold time after TCK rising TCK period RCK period Notes: 1. For DC electrical specifications of the JTAG pins (TCK, TDI, TMS, TDO, TRST), refer to Table 1-21 on page 1-36 when VDDP = 2.5 V and Table 1-22 on page 1-38 when VDDP = 3.3 V. 2. If RCK is being used, there is no minimum on the TCK period. Symbol tTCKTDI tTDOTCK tTCKTDO tTCK tRCK Min -4 10 0 100
2
Max 4
Unit ns ns ns
1,000 1,000
ns ns
100
TCK tTCK TMS, TDI tTCKTDI TDO tTDOTCK tTCKTDO
Figure 1-30 * JTAG Operation Timing
v5.7
1-53
ProASICPLUS Flash Family FPGAs
Embedded Memory Specifications
This section discusses ProASICPLUS SRAM/FIFO embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks (Table 1-49). Table 1-12 on page 1-23 shows basic SRAM and FIFO configurations. Simultaneous read and write to the same location must be done with care. On such accesses the DI bus is output to the DO bus. Refer to the ProASICPLUS RAM and FIFO Blocks application note for more information. * * * "Asynchronous SRAM Read, RDB Controlled" section on page 1-59 "Synchronous SRAM Write" Embedded Memory Specifications
Enclosed Timing Diagrams--SRAM Mode:
* "Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)" section on page 1-55 "Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)" section on page 1-56 "Asynchronous SRAM Write" section on page 1-57 "Asynchronous SRAM Read, Address Controlled, RDB=0" section on page 1-58
* * *
The difference between synchronous transparent and pipeline modes is the timing of all the output signals from the memory. In transparent mode, the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. If clock cycles are short (high clock speed), the data requires most of the clock cycle to change to valid values (stable signals). Processing of this data in the same clock cycle is nearly impossible. Most designers add registers at all outputs of the memory to push the data processing into the next clock cycle. An entire clock cycle can then be used to process the data. To simplify use of this memory setup, suitable registers have been implemented as part of the memory primitive and are available to the user in the synchronous pipeline mode. In this mode, the output signals will change shortly after the second rising edge, following the initiation of the read access.
Table 1-49 * Memory Block SRAM Interface Signals SRAM Signal WCLKS RCLKS RADDR<0:7> RBLKB RDB WADDR<0:7> WBLKB DI<0:8> WRB DO<0:8> RPE WPE PARODD Bits 1 1 8 1 1 8 1 9 1 9 1 1 1 In/Out In In In In In In In In In Out Out Out In Description Write clock used on synchronization on write side Read clock used on synchronization on read side Read address True read block select (active Low) True read pulse (active Low) Write address Write block select (active Low) Input data bits <0:8>, <8> can be used for parity In Negative true write pulse Output data bits <0:8>, <8> can be used for parity Out Read parity error (active High) Write parity error (active High) Selects Odd parity generation/detect when high, Even when low
Note: Not all signals shown are used in all modes.
1 -5 4
v5.7
ProASICPLUS Flash Family FPGAs
Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
RCLKS
Cycle Start
RBD, RBLKB
RADDR
New Valid Address
DO
Old Data Out
New Valid Data Out
RPE
tRACS tRDCS tRDCH tRACH tOCH tRPCH tCMH tOCA tRPCA tCCYC tCML
Note: The plot shows the normal operation status. Figure 1-31 * Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) Table 1-50 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx CCYC CMH CML OCA OCH RACH RACS RDCH RDCS RPCA RPCH Cycle time Clock high phase Clock low phase New DO access from RCLKS Old DO valid from RCLKS RADDR hold from RCLKS RADDR setup to RCLKS RDB hold from RCLKS RDB setup to RCLKS New RPE access from RCLKS Old RPE valid from RCLKS 0.5 1.0 0.5 1.0 9.5 3.0 Description Min. 7.5 3.0 3.0 7.5 3.0 Max. Units ns ns ns ns ns ns ns ns ns ns ns Notes
Note: All -F speed grade devices are 20% slower than the standard numbers.
v5.7
1-55
ProASICPLUS Flash Family FPGAs
Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
RCLKS
Cycle Start
RDB, RBLKB
RADDR
New Valid Address
DO
Old Data Out
New Valid Data Out
RPE
Old RPE Out
New RPE Out
tRACS tRACH tRDCH tRDCS tCMH tCCYC
Note: The plot shows the normal operation status. Figure 1-32 * Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) Table 1-51 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = 0C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx CCYC CMH CML OCA OCH RACH RACS RDCH RDCS RPCA RPCH Cycle time Clock high phase Clock low phase New DO access from RCLKS Old DO valid from RCLKS RADDR hold from RCLKS RADDR setup to RCLKS RDB hold from RCLKS RDB setup to RCLKS New RPE access from RCLKS Old RPE valid from RCLKS 0.5 1.0 0.5 1.0 4.0 1.0 Description Min. 7.5 3.0 3.0 2.0 0.75 Max. Units ns ns ns ns ns ns ns ns ns ns ns
tOCA tRPCH tOCH tRPCA tCML
Notes
Note: All -F speed grade devices are 20% slower than the standard numbers.
1 -5 6
v5.7
ProASICPLUS Flash Family FPGAs
Asynchronous SRAM Write
WADDR
WRB, WBLKB
DI
WPE
tAWRS
tAWRH tDWRH
tWPDA tDWRS tWRML tWRCYC
Note: The plot shows the normal operation status. Figure 1-33 * Asynchronous SRAM Write Table 1-52 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883B Symbol txxx AWRH AWRS DWRH DWRS DWRS WPDA WPDH WRCYC WRMH WRML Description WADDR hold from WB WADDR setup to WB DI hold from WB DI setup to WB DI setup to WB WPE access from DI WPE hold from DI Cycle time WB high phase WB low phase 7.5 3.0 3.0 Min. 1.0 0.5 1.5 0.5 2.5 3.0 1.0 Max. Units ns ns ns ns ns ns ns ns ns ns
tWPDH
tWRMH
Notes
PARGEN is inactive. PARGEN is active. WPE is invalid, while PARGEN is active.
Inactive Active
Note: All -F speed grade devices are 20% slower than the standard numbers.
v5.7
1-57
ProASICPLUS Flash Family FPGAs
Asynchronous SRAM Read, Address Controlled, RDB=0
RADDR
DO
RPE tOAH tRPAH tOAA tRPAA tACYC
Note: The plot shows the normal operation status. Figure 1-34 * Asynchronous SRAM Read, Address Controlled, RDB=0 Table 1-53 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883B Symbol txxx ACYC OAA OAH RPAA RPAH Description Read cycle time New DO access from RADDR stable Old DO hold from RADDR stable New RPE access from RADDR stable Old RPE hold from RADDR stable 10.0 3.0 Min. 7.5 7.5 3.0 Max. Units ns ns ns ns ns Notes
Note: All -F speed grade devices are 20% slower than the standard numbers.
1 -5 8
v5.7
ProASICPLUS Flash Family FPGAs
Asynchronous SRAM Read, RDB Controlled
RB=(RDB+RBLKB)
DO
RPE tORDH tRPRDH tORDA tRPRDA tRDML tRDCYC
Note: The plot shows the normal operation status. Figure 1-35 * Asynchronous SRAM Read, RDB Controlled Table 1-54 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx ORDA ORDH RDCYC RDMH RDML RPRDA RPRDH Description New DO access from RB Old DO valid from RB Read cycle time RB high phase RB low phase New RPE access from RB Old RPE valid from RB 7.5 3.0 3.0 9.5 3.0 Min. 7.5 3.0 Max. Units ns ns ns ns ns ns ns Inactive setup to new cycle Active Notes
tRDMH
Note: All -F speed grade devices are 20% slower than the standard numbers.
v5.7
1-59
ProASICPLUS Flash Family FPGAs
Synchronous SRAM Write
WCLKS
Cycle Start
WRB, WBLKB
WADDR, DI
WPE
tWRCH, tWBCH tWRCS, tWBCS tDCS, tWDCS tWPCH tDCH, tWACH tWPCA tCMH tCCYC tCML
Note: The plot shows the normal operation status. Figure 1-36 * Synchronous SRAM Write Table 1-55 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx CCYC CMH CML DCH DCS WACH WDCS WPCA WPCH Cycle time Clock high phase Clock low phase DI hold from WCLKS DI setup to WCLKS WADDR hold from WCLKS WADDR setup to WCLKS New WPE access from WCLKS Old WPE valid from WCLKS 0.5 1.0 Description Min. 7.5 3.0 3.0 0.5 1.0 0.5 1.0 3.0 0.5 Max. Units ns ns ns ns ns ns ns ns ns ns ns WPE is invalid while PARGEN is active Notes
WRCH, WBCH WRB & WBLKB hold from WCLKS WRCS, WBCS Notes: WRB & WBLKB setup to WCLKS
1. On simultaneous read and write accesses to the same location, DI is output to DO. 2. All -F speed grade devices are 20% slower than the standard numbers.
1 -6 0
v5.7
ProASICPLUS Flash Family FPGAs
Synchronous Write and Read to the Same Location
tCCYC tCMH RCLKS tCML
DO
Last Cycle Data
New Data*
WCLKS t WCLKRCLKH t WCLKRCLKS tOCH tOCA
* New data is read if WCLKS occurs before setup time. The data stored is read if WCLKS occurs after hold time. Note: The plot shows the normal operation status. Figure 1-37 * Synchronous Write and Read to the Same Location Table 1-56 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx CCYC CMH CML WCLKRCLKS WCLKRCLKH OCH OCA Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS and RCLKS driven by the same design signal. 3. If WCLKS changes after the hold time, the data will be read. 4. A setup or hold time violation will result in unknown output data. 5. All -F speed grade devices are 20% slower than the standard numbers. Cycle time Clock high phase Clock low phase WCLKS to RCLKS setup time WCLKS to RCLKS hold time Old DO valid from RCLKS New DO valid from RCLKS 7.5 Description Min. 7.5 3.0 3.0 - 0.1 7.0 3.0 Max. Units ns ns ns ns ns ns ns OCA/OCH displayed for Access Timed Output Notes
v5.7
1-61
ProASICPLUS Flash Family FPGAs
Asynchronous Write and Synchronous Read to the Same Location
t CMH RCLKS t CML
DO Last Cycle Data
New Data*
WB = {WRB + WBLKB}
DI t WRCKS t BRCLKH t OCH t OCA t DWRRCLKS tCCYC t DWRH
* New data is read if WB occurs before setup time. The stored data is read if WB occurs after hold time. Note: The plot shows the normal operation status. Figure 1-38 * Asynchronous Write and Synchronous Read to the Same Location Table 1-57 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx CCYC CMH CML WBRCLKS WBRCLKH OCH OCA DWRRCLKS DWRH Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be read. 3. A setup or hold time violation will result in unknown output data. 4. All -F speed grade devices are 20% slower than the standard numbers. Cycle time Clock high phase Clock low phase WB to RCLKS setup time WB to RCLKS hold time Old DO valid from RCLKS New DO valid from RCLKS DI to RCLKS setup time DI to WB hold time 7.5 0 1.5 Description Min. 7.5 3.0 3.0 -0.1 7.0 3.0 Max. Units ns ns ns ns ns ns ns ns ns OCA/OCH displayed Access Timed Output for Notes
1 -6 2
v5.7
ProASICPLUS Flash Family FPGAs
Asynchronous Write and Read to the Same Location
RB, RADDR
DO
OLD
NEW
NEWER
WB = {WRB+WBLKB} tORDA tORDH tRAWRS tOWRA tOWRH
Note: The plot shows the normal operation status. Figure 1-39 * Asynchronous Write and Read to the Same Location Table 1-58 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx ORDA ORDH OWRA OWRH RAWRS RAWRH Notes: 1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. Refer to the ProASICPLUS RAM and FIFO Blocks application note for more information. 2. Violation or RAWRS will disturb access to the OLD data. 3. Violation of RAWRH will disturb access to the NEWER data. 4. All -F speed grade devices are 20% slower than the standard numbers. Description New DO access from RB Old DO valid from RB New DO access from WB Old DO valid from WB RB or RADDR from WB RB or RADDR from WB 5.0 5.0 3.0 0.5 Min. 7.5 3.0 Max. Units ns ns ns ns ns ns Notes
tRAWRH
v5.7
1-63
ProASICPLUS Flash Family FPGAs
Synchronous Write and Asynchronous Read to the Same Location
RB, RADDR
DO
OLD
NEW
NEWER
WCLKS t ORDA t ORDH t OWRA t OWRH t RAWCLKS
Note: The plot shows the normal operation status. Figure 1-40 * Synchronous Write and Asynchronous Read to the Same Location Table 1-59 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx ORDA ORDH OWRA OWRH RAWCLKS RAWCLKH Notes: 1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. Violation of RAWCLKS will disturb access to OLD data. 3. Violation of RAWCLKH will disturb access to NEWER data. 4. All -F speed grade devices are 20% slower than the standard numbers. Description New DO access from RB Old DO valid from RB New DO access from WCLKS Old DO valid from WCLKS RB or RADDR from WCLKS RB or RADDR from WCLKS 5.0 5.0 3.0 0.5 Min. 7.5 3.0 Max. Units ns ns ns ns ns ns Notes
t RAWCLKH
1 -6 4
v5.7
ProASICPLUS Flash Family FPGAs
Asynchronous FIFO Full and Empty Transitions
The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem is created if the FIFO is written to during the transition from full to not full, or read during the transition from empty to not empty. The exact time at which the write or read operation changes from inhibited to accepted after the read (write) signal which causes the transition from full or empty to not full or not empty is indeterminate. For slow cycles, this indeterminate period starts 1 ns after the RB (WB) transition, which deactivates full or not empty and ends 3 ns after the RB (WB) transition. For fast cycles, the indeterminate period ends 3 ns (7.5 ns - RDL (WRL)) after the RB (WB) transition, whichever is later (Table 1-1 on page 1-7). The timing diagram for write is shown in Figure 1-38 on page 1-62. The timing diagram for read is shown in Figure 1-39 on page 1-63. For basic SRAM configurations, see Table 1-13 on page 1-24. When reset is asserted, the
Table 1-60 * Memory Block FIFO Interface Signals FIFO Signal WCLKS RCLKS LEVEL <0:7>* RBLKB RDB RESET WBLKB DI<0:8> WRB FULL, EMPTY EQTH, GEQTH* DO<0:8> RPE WPE LGDEP <0:2> PARODD Bits 1 1 8 1 1 1 1 9 1 2 2 9 1 1 3 1 In/Out In In In In In In In In In Out Out Out Out Out In In Description Write clock used for synchronization on write side Read clock used for synchronization on read side Direct configuration implements static flag logic Read block select (active Low) Read pulse (active Low) Reset for FIFO pointers (active Low) Write block select (active Low) Input data bits <0:8>, <8> will be generated if PARGEN is true Write pulse (active Low) FIFO flags. FULL prevents write and EMPTY prevents read EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more Output data bits <0:8> Read parity error (active High) Write parity error (active High) Configures DEPTH of the FIFO to 2 (LGDEP+1) Selects Odd parity generation/detect when high, Even when low
empty flag will be asserted, the counters will reset, the outputs go to zero, but the internal RAM is not erased.
Enclosed Timing Diagrams - FIFO Mode:
The following timing diagrams apply only to single cell; they are not applicable to cascaded cells. For more information, refer to the ProASICPLUS RAM/FIFO Blocks application note. * * * "Asynchronous FIFO Read" section on page 1-67 "Asynchronous FIFO Write" section on page 1-68 "Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)" section on page 1-69 "Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)" section on page 1-70 "Synchronous FIFO Write" section on page 1-71 "FIFO Reset" section on page 1-72
* * *
Note: *LEVEL is always eight bits (0000.0000, 0000.0001). That means for values of DEPTH greater than 256, not all values will be possible, e.g. for DEPTH=512, the LEVEL can only have the values 2, 4, . . ., 512. The LEVEL signal circuit will generate signals that indicate whether the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL. Since counting starts at 0, EQTH will become true when the FIFO holds (LEVEL+1) words for 512-bit FIFOs.
v5.7
1-65
ProASICPLUS Flash Family FPGAs
FULL RB Write cycle
Write inhibited
Write accepted
1 ns
3 ns WB
Note: All -F speed grade devices are 20% slower than the standard numbers. Figure 1-41 * Write Timing Diagram
EMPTY WB Read cycle
Read inhibited
Read accepted
1 ns
3 ns RB
Note: All -F speed grade devices are 20% slower than the standard numbers. Figure 1-42 * Read Timing Diagram
1 -6 6
v5.7
ProASICPLUS Flash Family FPGAs
Asynchronous FIFO Read
tRPRDA tRDL Cycle Start RB = (RDB+RBLKB) tRDH
RDATA
(Empty inhibits read)
RPE
WB
EMPTY
FULL
EQTH, GETH
tRDWRS tORDH tRPRDH tORDA tRPRDA tRDL tRDCYC tRDH tTHRDH tTHRDA
tERDH, tFRDH tERDA, tFRDA
Note: The plot shows the normal operation status. Figure 1-43 * Asynchronous FIFO Read Table 1-61 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. 0.5 3.01 3.0
1
Units ns ns ns ns
Notes Empty/full/thresh are invalid from the end of hold until the new access is complete
ERDH, FRDH, Old EMPTY, FULL, EQTH, & GETH valid hold THRDH time from RB ERDA FRDA ORDA ORDH RDCYC RDWRS RDH RDL RPRDA RPRDH THRDA Notes: New EMPTY access from RB FULL access from RB New DO access from RB Old DO valid from RB Read cycle time WB , clearing EMPTY, setup to RB RB high phase RB low phase New RPE access from RB Old RPE valid from RB EQTH or GETH access from RB 4.5 7.5 3.0
2
7.5 3.0
ns ns ns Enabling the read operation Inhibiting the read operation Inactive Active
1.0 3.0 3.0 9.5 4.0
ns ns ns ns ns ns
1. At fast cycles, ERDA and FRDA = MAX (7.5 ns - RDL), 3.0 ns. 2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns - WRL), 3.0 ns. 3. All -F speed grade devices are 20% slower than the standard numbers.
v5.7
1-67
ProASICPLUS Flash Family FPGAs
Asynchronous FIFO Write
WB = (WRB+WBLKB) Cycle Start
WDATA
(Full inhibits write)
WPE
RB
FULL
EMPTY
EQTH, GETH
tWRRDS tWPDA tDWRS tEWRH, tFWRH tEWRA, tFWRA tTHWRH tTHWRA tWRL tWRCYC tWRH
tDWRH tWPDH
Note: The plot shows the normal operation status. Figure 1-44 * Asynchronous FIFO Write Table 1-62 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx DWRH DWRS DWRS Description DI hold from WB DI setup to WB DI setup to WB Min. 1.5 0.5 2.5 0.5 3.01 3.01 4.5 3.0 1.0 7.5 3.02 1.0 3.0 3.0 ns ns Max. Units ns ns ns ns ns ns ns ns ns ns ns Enabling the write operation Inhibiting the write operation Inactive Active WPE is invalid while PARGEN is active PARGEN is inactive PARGEN is active Empty/full/thresh are invalid from the end of hold until the new access is complete Notes
EWRH, FWRH, Old EMPTY, FULL, EQTH, & GETH valid hold THWRH time after WB EWRA FWRA THWRA WPDA WPDH WRCYC WRRDS WRH WRL Notes: 1. 2. 3. 4. EMPTY access from WB New FULL access from WB EQTH or GETH access from WB WPE access from DI WPE hold from DI Cycle time RB , clearing FULL, setup to WB WB high phase WB low phase
At fast cycles, EWRA, FWRA = MAX (7.5 ns - WRL), 3.0 ns. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns - RDL), 3.0 ns. All -F speed grade devices are 20% slower than the standard numbers. After FIFO reset, WRB needs an initial falling edge prior to any write actions.
1 -6 8
v5.7
ProASICPLUS Flash Family FPGAs
Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
RCLK Cycle Start
RDB
RDATA
Old Data Out
New Valid Data Out (Empty Inhibits Read)
RPE
EMPTY
FULL
EQTH, GETH
tRDCH tRDCS tOCH tRPCH tOCA tRPCA tCMH tCCYC tCML tTHCBH tHCBA
tECBH, tFCBH tECBA, tFCBA
Note: The plot shows the normal operation status. Figure 1-45 * Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) Table 1-63 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx CCYC CMH CML ECBA FCBA Cycle time Clock high phase Clock low phase New EMPTY access from RCLKS FULL access from RCLKS Description Min. 7.5 3.0 3.0 3.01 3.01 1.0 7.5 3.0 0.5 1.0 9.5 3.0 4.5 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns Empty/full/thresh are invalid from the end of hold until the new access is complete Notes
ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold THCBH time from RCLKS OCA OCH RDCH RDCS RPCA RPCH HCBA Notes: New DO access from RCLKS Old DO valid from RCLKS RDB hold from RCLKS RDB setup to RCLKS New RPE access from RCLKS Old RPE valid from RCLKS EQTH or GETH access from RCLKS
1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMH), 3.0 ns. 2. All -F speed grade devices are 20% slower than the standard numbers.
v5.7
1-69
ProASICPLUS Flash Family FPGAs
Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
RCLK Cycle Start
RDB
RDATA
Old Data Out
New Valid Data Out
RPE
Old RPE Out
New RPE Out
EMPTY
FULL
EQTH, GETH
tECBH, tFCBH tRDCH tRDCS tTHCBH tHCBA tRPCA tCMH tCCYC tCML
tOCA tECBA, tFCBA tRPCH tOCH
Note: The plot shows the normal operation status. Figure 1-46 * Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) Table 1-64 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx CCYC CMH CML ECBA FCBA ECBH, THCBH OCA OCH RDCH RDCS RPCA RPCH HCBA Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMS), 3.0 ns. 2. All -F speed grade devices are 20% slower than the standard numbers. Cycle time Clock high phase Clock low phase New EMPTY access from RCLKS FULL access from RCLKS FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold time from RCLKS New DO access from RCLKS Old DO valid from RCLKS RDB hold from RCLKS RDB setup to RCLKS New RPE access from RCLKS Old RPE valid from RCLKS EQTH or GETH access from RCLKS 4.5 0.5 1.0 4.0 1.0 2.0 0.75 Description Min. 7.5 3.0 3.0 3.01 3.0
1
Max.
Units ns ns ns ns ns
Notes
1.0
ns ns ns ns ns ns ns ns
Empty/full/thresh are invalid from the end of hold until the new access is complete
1 -7 0
v5.7
ProASICPLUS Flash Family FPGAs
Synchronous FIFO Write
WCLKS Cycle Start
WRB, WBLKB
(Full Inhibits Write) DI
WPE
FULL
EMPTY
EQTH, GETH
tWRCH, tWBCH tWRCS, tWBCS tDCS tWPCH tDCH tWPCA tCMH tCCYC tCML tHCBA
tECBH, tFCBH tECBA, tFCBA tHCBH
Note: The plot shows the normal operation status. Figure 1-47 * Synchronous FIFO Write Table 1-65 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx CCYC CMH CML DCH DCS FCBA ECBA ECBH, FCBH, HCBH HCBA WPCA WPCH Cycle time Clock high phase Clock low phase DI hold from WCLKS DI setup to WCLKS New FULL access from WCLKS EMPTY access from WCLKS Old EMPTY, FULL, EQTH, & GETH valid hold time from WCLKS EQTH or GETH access from WCLKS New WPE access from WCLKS Old WPE valid from WCLKS 0.5 1.0 WRB & WBLKB setup to WCLKS 4.5 3.0 0.5 Description Min. 7.5 3.0 3.0 0.5 1.0 3.01 3.01 1.0 Max. Units ns ns ns ns ns ns ns ns Empty/full/thresh are invalid from the end of hold until the new access is complete Notes
ns ns ns ns ns WPE is invalid, while PARGEN is active
WRCH, WBCH WRB & WBLKB hold from WCLKS WRCS, WBCS Notes:
1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMH), 3.0 ns. 2. All -F speed grade devices are 20% slower than the standard numbers.
v5.7
1-71
ProASICPLUS Flash Family FPGAs
FIFO Reset
RESETB Cycle Start WRB/RBD1
WCLKS, RCLKS1
Cycle Start
FULL
EMPTY
EQTH, GETH
tCBRSS tERSA, tFRSA tTHRSA tRSL tWBRSS tCBRSH tWBRSH
Notes: 1. During reset, either the enables (WRB and RBD) OR the clocks (WCLKS and RCKLS) must be low. 2. The plot shows the normal operation status. Figure 1-48 * FIFO Reset Table 1-66 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx CBRSH1 CBRSS1 ERSA FRSA RSL THRSA WBRSH WBRSS Notes: 1. During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low. 2. All -F speed grade devices are 20% slower than the standard numbers.
1
Description WCLKS or RCLKS hold from RESETB WCLKS or RCLKS setup to RESETB New EMPTY access from RESETB FULL access from RESETB RESETB low phase EQTH or GETH access from RESETB WB hold from RESETB WB setup to RESETB
Min. 1.5 1.5 3.0 3.0 7.5 4.5 1.5 1.5
Max.
Units ns ns ns ns ns ns ns ns
Notes Synchronous mode only Synchronous mode only
Asynchronous mode only Asynchronous mode only
1
1 -7 2
v5.7
ProASICPLUS Flash Family FPGAs
Pin Description
User Pins
I/O User Input/Output
TMS
Test Mode Select
The TMS pin controls the use of boundary-scan circuitry. This pin has an internal pull-up resistor.
TCK Test Clock
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with standard LVTTL and LVCMOS specifications. Unused I/O pins are configured as inputs with pull-up resistors.
NC No Connect
Clock input pin for boundary scan (maximum 10 MHz). Actel recommends adding a nominal 20 k pull-up resistor to this pin.
TDI Test Data In
Serial input for boundary scan. A dedicated pull-up resistor is included to pull this pin high when not being driven.
TDO Test Data Out
To maintain compatibility with other Actel ProASICPLUS products, it is recommended that this pin not be connected to the circuitry on the board.
GL Global Pin
Serial output for boundary scan. Actel recommends adding a nominal 20k pull-up resistor to this pin.
TRST Test Reset Input
Low skew input pin for clock or other global signals. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as a normal I/O.
GLMX Global Multiplexing Pin
Asynchronous, active-low input pin for resetting boundary-scan circuitry. This pin has an internal pull-up resistor. For more information, please refer to Power-up Behavior of ProASICPLUS Devices application note.
Low skew input pin for clock or other global signals. This pin can be used in one of two special ways (refer to Actel's Using ProASICPLUS Clock Conditioning Circuits). When the external feedback option is selected for the PLL block, this pin is routed as the external feedback source to the clock conditioning circuit. In applications where two different signals access the same global net at different times through the use of GLMXx and GLMXLx macros, this pin will be fixed as one of the source pins. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as any normal I/O. If not used, the GLMXx pin will be configured as an input with pull-up.
Special Function Pins
RCK Running Clock
A free running clock is needed during programming if the programmer cannot guarantee that TCK will be uninterrupted. If not used, this pin has an internal pullup and can be left floating.
NPECL User Negative Input
Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected.
PPECL User Positive Input
Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected.
AVDD PLL Power Supply
Dedicated Pins
GND Ground
Common ground supply voltage.
VDD Logic Array Power Supply Pin
Analog VDD should be VDD (core voltage) 2.5 V (nominal) and be decoupled from GND with suitable decoupling capacitors to reduce noise. For more information, refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note. If the clock conditioning circuitry is not used in a design, AVDD can either be left floating or tied to 2.5 V.
AGND PLL Power Ground
2.5 V supply voltage.
VDDP I/O Pad Power Supply Pin
2.5 V or 3.3 V supply voltage.
The analog ground can be connected to the system ground. For more information, refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note. If the PLLs or clock conditioning circuitry are not used in a design, AGND should be tied to GND.
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ProASICPLUS Flash Family FPGAs VPP Programming Supply Pin
This pin may be connected to any voltage between GND and 16.5 V during normal operation, or it can be left unconnected.2 For information on using this pin during programming, see the In-System Programming ProASICPLUS Devices application note. Actel recommends floating the pin or connecting it to VDDP.
VPN Programming Supply Pin
finite length conductors that distribute the power to the device. This can be accomplished by providing sufficient bypass capacitance between the VPP and VPN pins and GND (using the shortest paths possible). Without sufficient bypass capacitance to counteract the inductance, the VPP and VPN pins may incur a voltage spike beyond the voltage that the device can withstand. This issue applies to all programming configurations. The solution prevents spikes from damaging the ProASICPLUS devices. Bypass capacitors are required for the VPP and VPN pads. Use a 0.01 F to 0.1 F ceramic capacitor with a 25 V or greater rating. To filter lowfrequency noise (decoupling), use a 4.7 F (low ESR, <1 <, tantalum, 25 V or greater rating) capacitor. The capacitors should be located as close to the device pins as possible (within 2.5 cm is desirable). The smaller, highfrequency capacitor should be placed closer to the device pins than the larger low-frequency capacitor. The same dual-capacitor circuit should be used on both the VPP and VPN pins (Figure 1-49).
This pin may be connected to any voltage between 0.5V and -13.8 V during normal operation, or it can be left unconnected.3 For information on using this pin during programming, see the In-System Programming ProASICPLUS Devices application note. Actel recommends floating the pin or connecting it to GND.
Recommended Design Practice for VPN/VPP
ProASICPLUS Devices - APA450, APA600, APA750, APA1000
Bypass capacitors are required from VPP to GND and VPN to GND for all ProASICPLUS devices during programming. During the erase cycle, ProASICPLUS devices may have current surges on the VPP and VPN power supplies. The only way to maintain the integrity of the power distribution to the ProASICPLUS device during these current surges is to counteract the inductance of the
2.5cm V
PP
ProASICPLUS Devices - APA075, APA150, APA300
These devices do not require bypass capacitors on the VPP and VPN pins as long as the total combined distance of the programming cable and the trace length on the board is less than or equal to 30 inches. Note: For trace lengths greater than 30 inches, use the bypass capacitor recommendations in the previous section.
+_ 0.1F to 0.01F 4.7F + Programming Header or Supplies _+ 0.1F to 0.01F
Actel PLUS ProASIC Device V
PN
4.7F +
Figure 1-49 * ProASICPLUS VPP and VPN Capacitor Requirements
2. There is a nominal 40 k pull-up resistor on VPP. 3. There is a nominal 40 k pull-down resistor on VPN.
1 -7 4
v5.7
ProASICPLUS Flash Family FPGAs
Package Pin Assignments
100-Pin TQFP
1
100
100-Pin TQFP
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
v5.7
2-1
ProASICPLUS Flash Family FPGAs
100-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 APA075 Function GND I/O I/O I/O I/O I/O I/O I/O GND I/O / GLMX1 I/O / GL1 AGND NPECL1 AVDD APA150 Function GND I/O I/O I/O I/O I/O I/O I/O GND I/O / GLMX1 I/O / GL1 AGND NPECL1 AVDD Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
100-Pin TQFP APA075 Function I/O VDD GND VDDP GND I/O I/O I/O I/O I/O I/O TCK TDI TMS VDDP GND VPP VPN TDO TRST RCK I/O I/O I/O I/O / GL3 APA150 Function I/O VDD GND VDDP GND I/O I/O I/O I/O I/O I/O TCK TDI TMS VDDP GND VPP VPN TDO TRST RCK I/O I/O I/O I/O / GL3 Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
100-Pin TQFP APA075 Function I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA150 Function I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP
PPECL1 / Input PPECL1 / Input I/O / GL2 VDD I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O / GL2 VDD I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O
PPECL2 / Input PPECL2 / Input AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 GND VDD I/O I/O AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 GND VDD I/O I/O
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ProASICPLUS Flash Family FPGAs
144-Pin TQFP
144 1
144-Pin TQFP
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
v5.7
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ProASICPLUS Flash Family FPGAs
144-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 APA075 Function I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O / GLMX1 I/O / GL1 AGND NPECL1 AVDD PPECL1 / Input I/O / GL2 I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O
144-Pin TQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 APA075 Function I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O TCK TDI TMS NC
144-Pin TQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 APA075 Function VPP VPN TDO TRST RCK I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O / GL3 PPECL2 / Input AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O
144-Pin TQFP Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 APA075 Function I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O
2 -4
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ProASICPLUS Flash Family FPGAs
208-Pin PQFP
1
208
208-Pin PQFP
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
v5.7
2-5
ProASICPLUS Flash Family FPGAs
208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 APA075 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O / GLMX1 I/O / GL2 AGND NPECL1 AVDD PPECL1 / Input GND I/O / GL1 I/O I/O I/O I/O I/O APA150 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O / GLMX1 I/O / GL2 AGND NPECL1 AVDD PPECL1 / Input GND I/O / GL1 I/O I/O I/O I/O I/O APA300 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O / GLMX1 I/O / GL2 AGND NPECL1 AVDD PPECL1 / Input GND I/O / GL1 I/O I/O I/O I/O I/O APA450 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O / GLMX1 I/O / GL2 AGND NPECL1 AVDD PPECL1 / Input GND I/O / GL1 I/O I/O I/O I/O I/O APA600 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O / GLMX1 I/O / GL2 AGND NPECL1 AVDD PPECL1 / Input GND I/O / GL1 I/O I/O I/O I/O I/O APA750 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O / GLMX1 I/O / GL2 AGND NPECL1 AVDD PPECL1 / Input GND I/O / GL1 I/O I/O I/O I/O I/O APA1000 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O / GLMX1 I/O / GL2 AGND NPECL1 AVDD PPECL1 / Input GND I/O / GL1 I/O I/O I/O I/O I/O
2 -6
v5.7
ProASICPLUS Flash Family FPGAs
208-Pin PQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 APA075 Function VDD I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O APA150 Function VDD I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O APA300 Function VDD I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O APA450 Function VDD I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O APA600 Function VDD I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O APA750 Function VDD I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O APA1000 Function VDD I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O
v5.7
2-7
ProASICPLUS Flash Family FPGAs
208-Pin PQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 APA075 Function VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND APA150 Function VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND APA300 Function VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND APA450 Function VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND APA600 Function VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND APA750 Function VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND APA1000 Function VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND
2 -8
v5.7
ProASICPLUS Flash Family FPGAs
208-Pin PQFP Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 APA075 Function VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD I/O I/O / GL3 PPECL2 / Input GND AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 I/O I/O VDDP I/O I/O APA150 Function VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD I/O I/O / GL3 PPECL2 / Input GND AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 I/O I/O VDDP I/O I/O APA300 Function VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD I/O I/O / GL3 PPECL2 / Input GND AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 I/O I/O VDDP I/O I/O APA450 Function VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD I/O I/O / GL3 PPECL2 / Input GND AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 I/O I/O VDDP I/O I/O APA600 Function VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD I/O I/O / GL3 PPECL2 / Input GND AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 I/O I/O VDDP I/O I/O APA750 Function VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD I/O I/O / GL3 PPECL2 / Input GND AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 I/O I/O VDDP I/O I/O APA1000 Function VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD I/O I/O / GL3 PPECL2 / Input GND AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 I/O I/O VDDP I/O I/O
v5.7
2-9
ProASICPLUS Flash Family FPGAs
208-Pin PQFP Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 APA075 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O APA150 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O APA300 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O APA450 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O APA600 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O APA750 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O APA1000 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O
2 -1 0
v5.7
ProASICPLUS Flash Family FPGAs
208-Pin PQFP Pin Number 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 APA075 Function I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA150 Function I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA300 Function I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA450 Function I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA600 Function I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA750 Function I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA1000 Function I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP
v5.7
2-11
ProASICPLUS Flash Family FPGAs
208-Pin CQFP
208 207 206 205 194 193 192 191 190 189 188 187 186 160 159 158 157
No. 1
1 2 3 4 156 155 154 153
Ceramic Tie Bar
31 32 33 34 35 36 37 38 39 142 141 140 139 138 137 136 135 134
208-Pin CQFP
49 50 51 52
108 107 106 105
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
2 -1 2
v5.7
101 102 103 104
53 54 55 57
84 85 86 87 88 89 90 91 92
ProASICPLUS Flash Family FPGAs
208-Pin CQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 APA300 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O / GLMX1 I/O / GL2 AGND NPECL1 AVDD APA600 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O / GLMX1 I/O / GL2 AGND NPECL1 AVDD APA1000 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O I/O VDDP I/O / GLMX1 I/O / GL2 AGND NPECL1 AVDD Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
208-Pin CQFP APA300 Function VDD I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O APA600 Function VDD I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O APA1000 Function VDD I/O I/O I/O VDDP GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O
PPECL1 / Input PPECL1 / Input PPECL1 / Input GND I/O / GL1 I/O I/O I/O I/O I/O GND I/O / GL1 I/O I/O I/O I/O I/O GND I/O / GL1 I/O I/O I/O I/O I/O
v5.7
2-13
ProASICPLUS Flash Family FPGAs
208-Pin CQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 APA300 Function VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND APA600 Function VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND APA1000 Function VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VDD VDDP I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O TCK TDI TMS VDDP GND Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
208-Pin CQFP APA300 Function VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD I/O I/O / GL3 APA600 Function VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD I/O I/O / GL3 APA1000 Function VPP VPN TDO TRST RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O VDD I/O I/O / GL3
PPECL2 / Input PPECL2 / Input PPECL2 / Input GND AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 I/O I/O VDDP I/O I/O GND AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 I/O I/O VDDP I/O I/O GND AVDD NPECL2 AGND I/O / GL4 I/O / GLMX2 I/O I/O VDDP I/O I/O
2 -1 4
v5.7
ProASICPLUS Flash Family FPGAs
208-Pin CQFP Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 APA300 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O APA600 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ]GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O APA1000 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O Pin Number 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
208-Pin CQFP APA300 Function I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA600 Function I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA1000 Function I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VDDP VDD I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP
v5.7
2-15
ProASICPLUS Flash Family FPGAs
352-Pin CQFP
268 267 266 265 352 351 350 349 339 338 337 336 335 334 333 332 331
1 2 3 4
Pin 1
264 263 262 261
Ceramic Tie Bar
41 42 43 44 45 46 47 48 49
352-Pin CQFP
223 222 221 220 219 218 217 216 215
85 86 87 88
180 179 178 177
89 90 91 92
127 128 129 130 131 132 133 134 135
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
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v5.7
173 174 175 176
ProASICPLUS Flash Family FPGAs
352-Pin CQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 APA300 Function I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O APA600 Function I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O Pin Number 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
352-Pin CQFP APA300 Function I/O / GLMX1 I/O / GL2 AGND AVDD NPECL1 APA600 Function I/O / GLMX1 I/O / GL2 AGND AVDD NPECL1 APA1000 Function I/O / GLMX1 I/O / GL2 AGND AVDD NPECL1
PPECL1 / Input PPECL1 / Input PPECL1 / Input I/O / GL1 I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O / GL1 I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O / GL1 I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O
v5.7
2-17
ProASICPLUS Flash Family FPGAs
352-Pin CQFP Pin Number 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 APA300 Function I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA600 Function I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA1000 Function I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP Pin Number 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148
352-Pin CQFP APA300 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O APA600 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O APA1000 Function GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O
2 -1 8
v5.7
ProASICPLUS Flash Family FPGAs
352-Pin CQFP Pin Number 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 APA300 Function I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O TCK TDI TMS I/O VPP VPN TDO TRST RCK I/O VDDP GND VDD APA600 Function I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O TCK TDI TMS I/O VPP VPN TDO TRST RCK I/O VDDP GND VDD APA1000 Function I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O TCK TDI TMS I/O VPP VPN TDO TRST RCK I/O VDDP GND VDD Pin Number 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222
352-Pin CQFP APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O / GL3 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O / GL3 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O / GL3
PPECL2 / Input PPECL2 / Input PPECL2 / Input
v5.7
2-19
ProASICPLUS Flash Family FPGAs
352-Pin CQFP Pin Number 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 APA300 Function NPECL2 AVDD AGND I/O / GL4 I/O / GLMX2 I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O APA600 Function NPECL2 AVDD AGND I/O / GL4 I/O / GLMX2 I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O APA1000 Function NPECL2 AVDD AGND I/O / GL4 I/O / GLMX2 I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD I/O Pin Number 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296
352-Pin CQFP APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND
2 -2 0
v5.7
ProASICPLUS Flash Family FPGAs
352-Pin CQFP Pin Number 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 APA300 Function VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O APA600 Function VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O APA1000 Function VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O Pin Number 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352
352-Pin CQFP APA300 Function I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP APA600 Function I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP APA1000 Function I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP
v5.7
2-21
ProASICPLUS Flash Family FPGAs
456-Pin PBGA
A1 Ball Pad Corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 54 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
2 -2 2
v5.7
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 APA150 Function VDDP VDDP NC NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC VDDP VDDP VDDP VDDP NC NC NC NC NC I/O APA300 Function VDDP VDDP NC NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC VDDP VDDP VDDP VDDP NC NC NC NC NC I/O APA450 Function VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP VDDP NC I/O I/O I/O I/O I/O APA600 Function VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O APA750 Function VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O APA1000 Function VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O
v5.7
2-23
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 APA150 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC VDDP VDDP VDDP NC VDDP NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC VDDP VDDP VDDP I/O VDDP NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
2 -2 4
v5.7
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 APA150 Function I/O I/O I/O I/O NC NC NC VDDP NC NC NC NC NC VDDP NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP NC APA300 Function I/O I/O I/O I/O NC NC NC VDDP NC NC NC NC I/O VDDP NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP I/O APA450 Function I/O I/O I/O I/O I/O I/O I/O VDDP NC NC NC NC I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O APA600 Function I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O
v5.7
2-25
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 APA150 Function NC NC NC NC NC NC VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD NC NC NC NC NC NC NC NC VDD VDD APA300 Function NC NC I/O I/O I/O I/O VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD APA450 Function NC NC I/O I/O I/O I/O VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD APA600 Function I/O I/O I/O I/O I/O I/O VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD APA750 Function I/O I/O I/O I/O I/O I/O VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD APA1000 Function I/O I/O I/O I/O I/O I/O VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD
2 -2 6
v5.7
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 APA150 Function NC NC NC NC I/O I/O NC NC VDD VDD NC NC NC I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
v5.7
2-27
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M11 M12 M13 APA150 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O / GL1 I/O / GL2 I/O I/O I/O GND GND GND APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O / GL1 I/O / GL2 I/O I/O I/O GND GND GND APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O / GL1 I/O / GL2 I/O I/O I/O GND GND GND APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O / GL1 I/O / GL2 I/O I/O I/O GND GND GND APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O / GL1 I/O / GL2 I/O I/O I/O GND GND GND APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O / GL1 I/O / GL2 I/O I/O I/O GND GND GND
2 -2 8
v5.7
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number M14 M15 M16 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13 P14 P15 APA150 Function GND GND GND I/O / GL4 I/O I/O I/O I/O I/O I/O / GLMX1 AGND PPECL1 / Input AVDD GND GND GND GND GND GND NPECL2 I/O / GL3 AVDD I/O / GLMX2 AGND I/O I/O I/O I/O NPECL1 GND GND GND GND GND APA300 Function GND GND GND I/O / GL4 I/O I/O I/O I/O I/O I/O / GLMX1 AGND PPECL1 / Input AVDD GND GND GND GND GND GND NPECL2 I/O / GL3 AVDD I/O / GLMX2 AGND I/O I/O I/O I/O NPECL1 GND GND GND GND GND APA450 Function GND GND GND I/O / GL4 I/O I/O I/O I/O I/O I/O / GLMX1 AGND PPECL1 / Input AVDD GND GND GND GND GND GND NPECL2 I/O / GL3 AVDD I/O / GLMX2 AGND I/O I/O I/O I/O NPECL1 GND GND GND GND GND APA600 Function GND GND GND I/O / GL4 I/O I/O I/O I/O I/O I/O / GLMX1 AGND PPECL1 / Input AVDD GND GND GND GND GND GND NPECL2 I/O / GL3 AVDD I/O / GLMX2 AGND I/O I/O I/O I/O NPECL1 GND GND GND GND GND APA750 Function GND GND GND I/O / GL4 I/O I/O I/O I/O I/O I/O / GLMX1 AGND PPECL1 / Input AVDD GND GND GND GND GND GND NPECL2 I/O / GL3 AVDD I/O / GLMX2 AGND I/O I/O I/O I/O NPECL1 GND GND GND GND GND APA1000 Function GND GND GND I/O / GL4 I/O I/O I/O I/O I/O I/O / GLMX1 AGND PPECL1 / Input AVDD GND GND GND GND GND GND NPECL2 I/O / GL3 AVDD I/O / GLMX2 AGND I/O I/O I/O I/O NPECL1 GND GND GND GND GND
v5.7
2-29
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 APA150 Function GND I/O I/O I/O I/O PPECL2 / Input I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O APA300 Function GND I/O I/O I/O I/O PPECL2 / Input I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O APA450 Function GND I/O I/O I/O I/O PPECL2 / Input I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O APA600 Function GND I/O I/O I/O I/O PPECL2 / Input I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O APA750 Function GND I/O I/O I/O I/O PPECL2 / Input I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O APA1000 Function GND I/O I/O I/O I/O PPECL2 / Input I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O
2 -3 0
v5.7
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 APA150 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O
v5.7
2-31
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 APA150 Function I/O I/O I/O NC VDD VDD NC NC NC NC I/O NC NC NC VDD VDD NC NC NC NC NC NC NC NC VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O APA300 Function I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O APA450 Function I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O APA600 Function I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O
2 -3 2
v5.7
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 APA150 Function I/O I/O I/O I/O I/O VDD VDD VDD NC NC NC NC NC NC NC VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO APA300 Function I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O NC I/O I/O I/O VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO APA450 Function I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O NC I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO APA600 Function I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO APA750 Function I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO APA1000 Function I/O I/O I/O I/O I/O VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO
v5.7
2-33
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 APA150 Function VDDP RCK NC NC NC NC VDDP NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC TCK VPP NC VDDP NC NC VDDP VDDP NC NC APA300 Function VDDP RCK NC I/O NC I/O VDDP NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC TCK VPP NC VDDP NC NC VDDP VDDP NC NC APA450 Function VDDP RCK I/O I/O NC I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP NC VDDP I/O I/O VDDP VDDP I/O I/O APA600 Function VDDP RCK I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP I/O VDDP I/O I/O VDDP VDDP I/O I/O APA750 Function VDDP RCK I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP I/O VDDP I/O I/O VDDP VDDP I/O I/O APA1000 Function VDDP RCK I/O I/O I/O I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP I/O VDDP I/O I/O VDDP VDDP I/O I/O
2 -3 4
v5.7
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 APA150 Function NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC VPN TRST VDDP VDDP VDDP VDDP NC NC NC NC NC NC I/O I/O I/O I/O APA300 Function NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC VPN TRST VDDP VDDP VDDP VDDP NC NC NC NC NC NC I/O I/O I/O I/O APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VPN TRST VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O NC I/O I/O I/O I/O APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VPN TRST VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VPN TRST VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VPN TRST VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
v5.7
2-35
ProASICPLUS Flash Family FPGAs
456-Pin PBGA Pin Number AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 APA150 Function I/O I/O I/O I/O I/O NC NC NC NC NC TDI NC VDDP VDDP APA300 Function I/O I/O I/O I/O I/O NC NC NC NC NC TDI NC VDDP VDDP APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O VDDP VDDP APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O VDDP VDDP APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O VDDP VDDP APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O VDDP VDDP
2 -3 6
v5.7
ProASICPLUS Flash Family FPGAs
144-Pin FBGA
A1 Ball Pad Corner 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
v5.7
2-37
ProASICPLUS Flash Family FPGAs
144-FBGA Pin Pin APA075 Number Function A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 I/O I/O I/O I/O I/O GND I/O VDD I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O / GL1 I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O APA150 Function I/O I/O I/O I/O I/O GND I/O VDD I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O / GL1 I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O APA300 Function I/O I/O I/O I/O I/O GND I/O VDD I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O / GL1 I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O APA450 Function I/O I/O I/O I/O I/O GND I/O VDD I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O / GL1 I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O F12 Pin APA075 Number Function D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
144-FBGA Pin APA150 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 VDD I/O I/O VDDP I/O VDDP VDDP AVDD VDDP VDD NPECL2 AGND I/O / GL2 AGND VDD I/O I/O VDDP I/O VDDP VDDP AVDD VDDP VDD NPECL2 AGND I/O / GL2 AGND VDD I/O I/O VDDP I/O VDDP VDDP AVDD VDDP VDD NPECL2 AGND I/O / GL2 AGND VDD I/O I/O VDDP I/O VDDP VDDP AVDD VDDP VDD NPECL2 AGND I/O / GL2 AGND
I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O GND GND GND I/O I/O / GL4 GND PPECL2 / Input I/O / GL3 I/O GND GND GND I/O I/O / GL4 GND PPECL2 / Input I/O / GL3 I/O GND GND GND I/O I/O / GL4 GND PPECL2 / Input I/O / GL3 I/O GND GND GND I/O I/O / GL4 GND PPECL2 / Input I/O / GL3
2 -3 8
v5.7
ProASICPLUS Flash Family FPGAs
144-FBGA Pin Pin APA075 Number Function G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 PPECL1 / Input GND AVDD NPECL1 GND GND GND I/O I/O I/O I/O I/O VDD I/O I/O I/O VDD I/O I/O I/O I/O VDDP I/O VDD I/O I/O VDDP I/O I/O I/O VDD TCK I/O TDO I/O I/O APA150 Function PPECL1 / Input GND AVDD NPECL1 GND GND GND I/O I/O I/O I/O I/O VDD I/O I/O I/O VDD I/O I/O I/O I/O VDDP I/O VDD I/O I/O VDDP I/O I/O I/O VDD TCK I/O TDO I/O I/O APA300 Function PPECL1 / Input GND AVDD NPECL1 GND GND GND I/O I/O I/O I/O I/O VDD I/O I/O I/O VDD I/O I/O I/O I/O VDDP I/O VDD I/O I/O VDDP I/O I/O I/O VDD TCK I/O TDO I/O I/O APA450 Function PPECL1 / Input GND AVDD NPECL1 GND GND GND I/O I/O I/O I/O I/O VDD I/O I/O I/O VDD I/O I/O I/O I/O VDDP I/O VDD I/O I/O VDDP I/O I/O I/O VDD TCK I/O TDO I/O I/O Pin APA075 Number Function K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O I/O VDDP I/O I/O I/O TMS RCK I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O TDI VDDP VPP VPN
144-FBGA Pin APA150 Function I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O I/O VDDP I/O I/O I/O TMS RCK I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O TDI VDDP VPP VPN APA300 Function I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O I/O VDDP I/O I/O I/O TMS RCK I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O TDI VDDP VPP VPN APA450 Function I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O I/O VDDP I/O I/O I/O TMS RCK I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O TDI VDDP VPP VPN
v5.7
2-39
ProASICPLUS Flash Family FPGAs
256-Pin FBGA
A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
2 -4 0
v5.7
ProASICPLUS Flash Family FPGAs
256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 APA150 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA300 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA450 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA600 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6
256-Pin FBGA APA150 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP
v5.7
2-41
ProASICPLUS Flash Family FPGAs
256-Pin FBGA Pin Number E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 APA150 Function VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND APA300 Function VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND APA450 Function VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND APA600 Function VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND J3 J4 J5 J6 J7 J8 J9 J10 J11 Pin Number G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2
256-Pin FBGA APA150 Function GND VDD VDDP I/O I/O I/O I/O I/O / GL1 NPECL1 APA300 Function GND VDD VDDP I/O I/O I/O I/O I/O / GL1 NPECL1 APA450 Function GND VDD VDDP I/O I/O I/O I/O I/O / GL1 NPECL1 APA600 Function GND VDD VDDP I/O I/O I/O I/O I/O / GL1 NPECL1
I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 AGND I/O VDD GND GND GND GND VDD I/O AGND I/O VDD GND GND GND GND VDD I/O AGND I/O VDD GND GND GND GND VDD I/O AGND I/O VDD GND GND GND GND VDD I/O
I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 NPECL2 AGND I/O / GL4 I/O / GL2 PPECL1 / Input AVDD I/O I/O VDD GND GND GND GND VDD NPECL2 AGND I/O / GL4 I/O / GL2 PPECL1 / Input AVDD I/O I/O VDD GND GND GND GND VDD NPECL2 AGND I/O / GL4 I/O / GL2 PPECL1 / Input AVDD I/O I/O VDD GND GND GND GND VDD NPECL2 AGND I/O / GL4 I/O / GL2 PPECL1 / Input AVDD I/O I/O VDD GND GND GND GND VDD
2 -4 2
v5.7
ProASICPLUS Flash Family FPGAs
256-Pin FBGA Pin Number J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 APA150 Function I/O PPECL2 / Input I/O AVDD I/O / GL3 I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O APA300 Function I/O PPECL2 / Input I/O AVDD I/O / GL3 I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O APA450 Function I/O PPECL2 / Input I/O AVDD I/O / GL3 I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O APA600 Function I/O PPECL2 / Input I/O AVDD I/O / GL3 I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O Pin Number L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16
256-Pin FBGA APA150 Function I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O
v5.7
2-43
ProASICPLUS Flash Family FPGAs
256-Pin FBGA Pin Number P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 APA150 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND I/O I/O APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND I/O I/O APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND I/O I/O APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND I/O I/O Pin Number T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
256-Pin FBGA APA150 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND APA300 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND
2 -4 4
v5.7
ProASICPLUS Flash Family FPGAs
484-Pin FBGA
A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
v5.7
2-45
ProASICPLUS Flash Family FPGAs
484-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 APA450 Function GND GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND GND GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA600 Function GND GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND GND GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6
484-Pin FBGA APA450 Function I/O I/O I/O I/O I/O I/O VDDP GND VDDP NC I/O I/O GND I/O I/O VDD VDD I/O I/O NC NC VDD VDD NC I/O GND I/O I/O I/O VDDP I/O I/O NC GND I/O I/O APA600 Function I/O I/O I/O I/O I/O I/O VDDP GND VDDP I/O I/O I/O GND I/O I/O VDD VDD I/O I/O I/O I/O VDD VDD I/O I/O GND I/O I/O I/O VDDP I/O I/O I/O GND I/O I/O Pin Number D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20
484-Pin FBGA APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O NC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
2 -4 6
v5.7
ProASICPLUS Flash Family FPGAs
484-Pin FBGA Pin Number E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4
484-Pin FBGA APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O NC I/O APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O Pin Number J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18
484-Pin FBGA APA450 Function I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O APA600 Function I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O
v5.7
2-47
ProASICPLUS Flash Family FPGAs
484-Pin FBGA Pin Number K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 APA450 Function I/O I/O I/O I/O NC I/O I/O I/O / GL1 NPECL1 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O / GL1 NPECL1 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 Pin Number M10 M11 M12 M13 M14 M15 M16
484-Pin FBGA APA450 Function GND GND GND GND VDD I/O PPECL2 / Input I/O AVDD I/O / GL3 I/O I/O I/O I/O I/O NC I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O NC I/O I/O APA600 Function GND GND GND GND VDD I/O PPECL2 / Input I/O AVDD I/O / GL3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O Pin Number P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14
484-Pin FBGA APA450 Function I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O NC I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP APA600 Function I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O VDDP VDDP I/O I/O VDDP VDDP
I/O / GLMX1 I/O / GLMX1 AGND I/O VDD GND GND GND GND VDD I/O AGND I/O VDD GND GND GND GND VDD I/O
I/O / GLMX2 I/O / GLMX2 NPECL2 AGND I/O / GL4 I/O I/O I/O I/O I/O I/O I/O / GL2 PPECL1 / Input AVDD I/O I/O VDD NPECL2 AGND I/O / GL4 I/O I/O I/O I/O I/O I/O I/O / GL2 PPECL1 / Input AVDD I/O I/O VDD
2 -4 8
v5.7
ProASICPLUS Flash Family FPGAs
484-Pin FBGA Pin Number R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 APA450 Function I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O APA600 Function I/O I/O I/O I/O I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20
484-Pin FBGA APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O NC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK VPP TRST I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN TDO GND Pin Number V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12
484-Pin FBGA APA450 Function NC I/O NC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND NC NC I/O VDDP I/O I/O I/O GND I/O I/O VDD VDD I/O I/O I/O APA600 Function I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS GND I/O I/O I/O VDDP I/O I/O I/O GND I/O I/O VDD VDD I/O I/O I/O
v5.7
2-49
ProASICPLUS Flash Family FPGAs
484-Pin FBGA Pin Number Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 APA450 Function I/O VDD VDD I/O I/O GND I/O I/O NC VDDP GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O VDDP GND GND GND VDDP I/O APA600 Function I/O VDD VDD I/O I/O GND I/O I/O I/O VDDP GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND GND GND VDDP I/O Pin Number AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22
484-Pin FBGA APA450 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O VDDP GND GND APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND GND
2 -5 0
v5.7
ProASICPLUS Flash Family FPGAs
676-Pin FBGA
A1 Ball Pad Corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 54 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
v5.7
2-51
ProASICPLUS Flash Family FPGAs
676-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 APA600 Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O APA750 Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O Pin Number B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18
676-Pin FBGA APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1
676-Pin FBGA APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
2 -5 2
v5.7
ProASICPLUS Flash Family FPGAs
676-Pin FBGA Pin Number E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O NC I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O NC I/O I/O I/O Pin Number F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19
676-Pin FBGA APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD NC I/O NC I/O NC I/O NC I/O NC I/O VDDP APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD NC I/O NC I/O NC I/O NC I/O NC I/O VDDP Pin Number G20 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 J1 J2
676-Pin FBGA APA600 Function NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O
v5.7
2-53
ProASICPLUS Flash Family FPGAs
676-Pin FBGA Pin Number J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 APA600 Function I/O I/O I/O I/O NC VDDP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND APA750 Function I/O I/O I/O I/O NC VDDP VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND Pin Number K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20
676-Pin FBGA APA600 Function GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC APA750 Function GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC Pin Number L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 N1 N2 N3
676-Pin FBGA APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O / GL1 AGND APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O / GL1 AGND
I/O / GLMX1 I/O / GLMX1
2 -5 4
v5.7
ProASICPLUS Flash Family FPGAs
676-Pin FBGA Pin Number N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 APA600 Function I/O NPECL1 I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O / GL3 I/O NPECL2 I/O / GL4 I/O I/O / GL2 AVDD I/O I/O PPECL1 / Input I/O I/O VDDP VDD GND GND APA750 Function I/O NPECL1 I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O / GL3 I/O NPECL2 I/O / GL4 I/O I/O / GL2 AVDD I/O I/O PPECL1 / Input I/O I/O VDDP VDD GND GND P25 P26 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 Pin Number P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24
676-Pin FBGA APA600 Function GND GND GND GND GND GND VDD VDDP I/O I/O APA750 Function GND GND GND GND GND GND VDD VDDP I/O I/O Pin Number R20 R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 U1 U2
676-Pin FBGA APA600 Function NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O / GLMX2 I/O / GLMX2 I/O PPECL2 / Input AVDD AGND I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O PPECL2 / Input AVDD AGND I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP
v5.7
2-55
ProASICPLUS Flash Family FPGAs
676-Pin FBGA Pin Number U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 APA600 Function I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD VDD VDD APA750 Function I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD VDD VDD Pin Number V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20
676-Pin FBGA APA600 Function VDD VDD VDD VDD VDD VDD VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDD VDDP APA750 Function VDD VDD VDD VDD VDD VDD VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDD VDDP Pin Number W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3
676-Pin FBGA APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP NC I/O NC I/O NC I/O NC I/O NC I/O VDD VPP I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP NC I/O NC I/O NC I/O NC I/O NC I/O VDD VPP I/O I/O I/O I/O I/O I/O I/O I/O I/O
2 -5 6
v5.7
ProASICPLUS Flash Family FPGAs
676-Pin FBGA Pin Number AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 APA600 Function I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO GND GND I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O APA750 Function I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO GND GND I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O Pin Number AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21
676-Pin FBGA APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O TCK TRST I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O TCK TRST I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4
676-Pin FBGA APA600 Function TMS RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN I/O I/O GND GND GND I/O APA750 Function TMS RCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI VPN I/O I/O GND GND GND I/O
v5.7
2-57
ProASICPLUS Flash Family FPGAs
676-Pin FBGA Pin Number AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26
676-Pin FBGA APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND
2 -5 8
v5.7
ProASICPLUS Flash Family FPGAs
896-Pin FBGA
A1 Ball Pad Corner 3029 2827 2625 2423 22 2120191817 16 151413 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
v5.7
2-59
ProASICPLUS Flash Family FPGAs
896-Pin FBGA Pin Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B1 B2 B3 B4 B5 B6 APA750 Function GND GND I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GND I/O GND GND GND GND I/O VDD I/O VDD APA1000 Function GND GND I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GND I/O GND GND GND GND I/O VDD I/O VDD Pin Number B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
896-Pin FBGA APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDD I/O GND GND GND I/O VDD I/O VDDP I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDD I/O GND GND GND I/O VDD I/O VDDP I/O I/O I/O I/O I/O Pin Number C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
896-Pin FBGA APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD NC GND I/O VDD I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O GND I/O VDD I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
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v5.7
ProASICPLUS Flash Family FPGAs
896-Pin FBGA Pin Number D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VDD I/O GND I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VDD I/O GND I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22
896-Pin FBGA APA750 Function I/O I/O I/O I/O I/O VDDP I/O VDD I/O VDDP I/O GND I/O VDD I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O VDDP I/O VDD I/O VDDP I/O GND I/O VDD I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number F23 F24 F25 F26 F27 F28 F29 F30 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26
896-Pin FBGA APA750 Function I/O I/O GND I/O I/O I/O VDD I/O GND I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O VDDP APA1000 Function I/O I/O GND I/O I/O I/O VDD I/O GND I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O VDDP
v5.7
2-61
ProASICPLUS Flash Family FPGAs
896-Pin FBGA Pin Number G27 G28 G29 G30 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 APA750 Function I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O Pin Number J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 K1 K2 K3 K4
896-Pin FBGA APA750 Function I/O I/O I/O I/O I/O I/O VDDP I/O VDD NC NC NC NC NC NC NC NC NC NC NC NC VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 L1 L2 L3 L4 L5 L6 L7 L8
896-Pin FBGA APA750 Function I/O I/O I/O I/O NC VDD NC VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP NC VDD NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O VDD I/O VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
2 -6 2
v5.7
ProASICPLUS Flash Family FPGAs
896-Pin FBGA Pin Number L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 APA750 Function NC NC VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDD GND APA1000 Function I/O I/O VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND Pin Number M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16
896-Pin FBGA APA750 Function GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND APA1000 Function GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND Pin Number N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20
896-Pin FBGA APA750 Function GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD APA1000 Function GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD
v5.7
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ProASICPLUS Flash Family FPGAs
896-Pin FBGA Pin Number P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 APA750 Function VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O / GLMX1 AGND NPECL1 I/O / GL1 I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O APA1000 Function VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O / GLMX1 AGND NPECL1 I/O / GL1 I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O Pin Number R25 R26 R27 R28 R29 R30 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28
896-Pin FBGA APA750 Function I/O I/O NPECL2 AGND I/O / GLMX2 I/O I/O AVDD I/O / GL2 APA1000 Function I/O I/O NPECL2 AGND I/O / GLMX2 I/O I/O AVDD I/O / GL2 Pin Number T29 T30 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 V1 V2
896-Pin FBGA APA750 Function AVDD I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function AVDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
PPECL1 / Input PPECL1 / Input I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O
PPECL2 / Input PPECL2 / Input I/O / GL4 I/O / GL3 I/O / GL4 I/O / GL3
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v5.7
ProASICPLUS Flash Family FPGAs
896-Pin FBGA Pin Number V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 W1 W2 W3 W4 W5 W6 APA750 Function I/O I/O I/O I/O I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10
896-Pin FBGA APA750 Function I/O I/O NC VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC APA1000 Function I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14
896-Pin FBGA APA750 Function VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC VDD NC VDDP VDDP VDDP APA1000 Function VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP VDDP VDDP
v5.7
2-65
ProASICPLUS Flash Family FPGAs
896-Pin FBGA Pin Number AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 APA750 Function VDDP VDDP VDDP VDDP VDDP NC VDD NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD NC NC NC NC NC NC NC NC NC APA1000 Function VDDP VDDP VDDP VDDP VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22
896-Pin FBGA APA750 Function NC NC NC VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC APA1000 Function I/O I/O I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26
896-Pin FBGA APA750 Function GND I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP TCK VDD TRST VDDP APA1000 Function GND I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP TCK VDD TRST VDDP
2 -6 6
v5.7
ProASICPLUS Flash Family FPGAs
896-Pin FBGA Pin Number AD27 AD28 AD29 AD30 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 APA750 Function I/O I/O I/O GND I/O VDD I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDD I/O APA1000 Function I/O I/O I/O GND I/O VDD I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDD I/O Pin Number AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AG1 AG2 AG3 AG4
896-Pin FBGA APA750 Function GND I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD TDO VDDP VPN GND I/O VDD I/O GND APA1000 Function GND I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD TDO VDDP VPN GND I/O VDD I/O GND Pin Number AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8
896-Pin FBGA APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND RCK VDD I/O GND I/O VDD I/O VDDP I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND RCK VDD I/O GND I/O VDD I/O VDDP I/O I/O I/O
v5.7
2-67
ProASICPLUS Flash Family FPGAs
896-Pin FBGA Pin Number AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP TDI VDD VPP GND GND GND I/O VDD I/O VDD I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP TDI VDD VPP GND GND GND I/O VDD I/O VDD I/O I/O I/O I/O I/O I/O Pin Number AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17
896-Pin FBGA APA750 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDD TMS GND GND GND GND I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDD TMS GND GND GND GND I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29
896-Pin FBGA APA750 Function I/O I/O I/O I/O I/O I/O GND I/O GND I/O GND GND APA1000 Function I/O I/O I/O I/O I/O I/O GND I/O GND I/O GND GND
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v5.7
ProASICPLUS Flash Family FPGAs
1152-Pin FBGA
A1 Ball Pad Corner 34 3332 3130 2928 2726 2524 232221 2019 18 171615 1413 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
v5.7
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ProASICPLUS Flash Family FPGAs
1152-Pin FBGA Pin Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 B1 B2 B3 B4 B5 APA1000 Function NC GND GND GND I/O VDD VDD VDD VDD I/O GND I/O VDDP VDDP I/O GND GND I/O VDDP VDDP I/O GND I/O VDD VDD VDD VDD I/O GND GND GND NC NC NC GND GND GND
1152-Pin FBGA Pin Number B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 C1 C2 C3 C4 C5 C6 C7 C8 APA1000 Function NC I/O NC I/O NC I/O GND I/O VDDP VDDP I/O GND GND I/O VDDP VDDP I/O GND I/O NC I/O NC I/O NC GND GND GND NC NC GND GND NC GND GND I/O GND I/O
1152-Pin FBGA Pin Number C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 APA1000 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GND I/O GND GND NC GND GND GND GND GND GND I/O VDD I/O VDD I/O I/O I/O
1152-Pin FBGA Pin Number D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDD I/O GND GND GND GND GND GND GND I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O
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v5.7
ProASICPLUS Flash Family FPGAs
1152-Pin FBGA Pin Number E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O GND GND GND I/O NC I/O VDD I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
1152-Pin FBGA Pin Number F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VDD I/O NC NC VDD I/O GND I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
1152-Pin FBGA Pin Number G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 APA1000 Function I/O I/O I/O I/O I/O VDDP I/O VDD I/O VDDP I/O GND I/O VDD VDD NC I/O VDD I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
1152-Pin FBGA Pin Number H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 APA1000 Function I/O I/O I/O GND I/O I/O I/O VDD I/O NC VDD VDD I/O GND I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD
v5.7
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ProASICPLUS Flash Family FPGAs
1152-Pin FBGA Pin Number J27 J28 J29 J30 J31 J32 J33 J34 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 APA1000 Function I/O VDDP I/O I/O I/O GND I/O VDD VDD NC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O
1152-Pin FBGA Pin Number K30 K31 K32 K33 K34 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 APA1000 Function I/O I/O I/O NC VDD I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O
1152-Pin FBGA Pin Number L33 L34 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 M34 N1 APA1000 Function I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O
1152-Pin FBGA Pin Number N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 N31 N32 N33 N34 P1 P2 P3 P4 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O
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ProASICPLUS Flash Family FPGAs
1152-Pin FBGA Pin Number P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 R1 R2 R3 R4 R5 R6 R7 APA1000 Function I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O
1152-Pin FBGA Pin Number R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 APA1000 Function I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
1152-Pin FBGA Pin Number T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 APA1000 Function I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O / GLMX1 AGND NPECL1 I/O / GL1 I/O I/O I/O I/O VDDP VDD
1152-Pin FBGA Pin Number U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 APA1000 Function GND GND GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O NPECL2 AGND I/O / GLMX2 I/O GND GND GND GND I/O AVDD I/O / GL2 PPECL1 / Input I/O I/O I/O I/O I/O VDDP VDD GND GND
v5.7
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ProASICPLUS Flash Family FPGAs
1152-Pin FBGA Pin Number V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 APA1000 Function GND GND GND GND GND GND VDD VDDP I/O I/O I/O I/O PPECL2 / Input I/O / GL4 I/O / GL3 AVDD I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND
1152-Pin FBGA Pin Number W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W33 W34 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 APA1000 Function GND GND GND GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND
1152-Pin FBGA Pin Number Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 APA1000 Function GND VDD VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDD GND GND GND GND GND GND GND GND VDD VDDP
1152-Pin FBGA Pin Number AA24 AA25 AA26 AA27 AA28 AA29 AA30 AA31 AA32 AA33 AA34 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD I/O I/O I/O I/O
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v5.7
ProASICPLUS Flash Family FPGAs
1152-Pin FBGA Pin Number AB27 AB28 AB29 AB30 AB31 AB32 AB33 AB34 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP I/O VDD I/O I/O I/O I/O I/O I/O
1152-Pin FBGA Pin Number AC30 AC31 AC32 AC33 AC34 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 APA1000 Function I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O
1152-Pin FBGA Pin Number AD33 AD34 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AE33 AE34 AF1 APA1000 Function I/O I/O VDD NC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O NC VDD VDD
1152-Pin FBGA Pin Number AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AG1 AG2 AG3 AG4 APA1000 Function I/O GND I/O I/O I/O VDDP I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP TCK VDD TRST VDDP I/O I/O I/O GND I/O VDD VDD NC I/O VDD
v5.7
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ProASICPLUS Flash Family FPGAs
1152-Pin FBGA Pin Number AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AG32 AG33 AG34 AH1 AH2 AH3 AH4 AH5 AH6 AH7 APA1000 Function I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDD I/O NC VDD VDD I/O GND I/O VDDP I/O VDD
1152-Pin FBGA Pin Number AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 APA1000 Function I/O VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP I/O VDD TDO VDDP VPN GND I/O VDD I/O NC I/O VDD I/O GND I/O I/O I/O I/O
1152-Pin FBGA Pin Number AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND RCK VDD I/O NC NC GND GND GND I/O VDD I/O VDDP I/O I/O I/O I/O I/O I/O
1152-Pin FBGA Pin Number AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP TDI VDD VPP GND GND GND GND GND GND GND I/O VDD I/O VDD I/O I/O I/O I/O I/O I/O I/O I/O
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v5.7
ProASICPLUS Flash Family FPGAs
1152-Pin FBGA Pin Number AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD I/O VDD TMS GND GND GND GND GND GND NC GND GND I/O GND I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
1152-Pin FBGA Pin Number AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 APA1000 Function I/O I/O I/O I/O I/O I/O GND I/O GND I/O GND GND NC GND GND NC NC GND GND GND NC I/O NC I/O NC I/O GND I/O VDDP VDDP I/O GND GND I/O VDDP VDDP I/O
1152-Pin FBGA Pin Number AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 APA1000 Function GND I/O NC I/O NC I/O NC GND GND GND NC NC NC GND GND GND I/O VDD VDD VDD VDD I/O GND I/O VDDP VDDP I/O GND GND I/O VDDP VDDP I/O GND I/O VDD VDD
1152-Pin FBGA Pin Number AP27 AP28 AP29 AP30 AP31 AP32 AP33 APA1000 Function VDD VDD I/O GND GND GND NC
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ProASICPLUS Flash Family FPGAs
624-Pin CCGA/LGA
Top View
D A1 Corner Index Area A A2 A1 b
E
Side View
D1 e
AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 101112131415 161718 19 20 2122 2324 25
E1
e
Bottom View
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/solutions/package/docs.aspx.
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v5.7
ProASICPLUS Flash Family FPGAs
624-Pin CCGA/LGA Pin Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND I/O GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O
624-Pin CCGA/LGA Pin Number B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O VDDP GND VDD I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O VDDP GND VDD I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O
624-Pin CCGA/LGA Pin Number C22 C23 C24 C25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 E1 E2 E3 E4 E5 E6 APA600 Function I/O GND VDD I/O I/O I/O VDD GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O GND VDD I/O I/O I/O VDD GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
v5.7
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ProASICPLUS Flash Family FPGAs
624-Pin CCGA/LGA Pin Number E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O
624-Pin CCGA/LGA Pin Number F17 F18 F19 F20 F21 F22 F23 F24 F25 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 H1 APA600 Function I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
624-Pin CCGA/LGA Pin Number H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 APA600 Function I/O GND I/O I/O I/O I/O VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O GND I/O VDDP GND GND GND APA1000 Function I/O GND I/O I/O I/O I/O VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O GND I/O VDDP GND GND GND
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v5.7
ProASICPLUS Flash Family FPGAs
624-Pin CCGA/LGA Pin Number J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 APA600 Function GND GND GND GND GND GND VDDP I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD VDD VDD VDD GND VDDP I/O I/O I/O APA1000 Function GND GND GND GND GND GND VDDP I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD VDD VDD VDD VDD VDD VDD GND VDDP I/O I/O I/O
624-Pin CCGA/LGA Pin Number K22 K23 K24 K25 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 M1 M2 M3 M4 M5 M6 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD GND GND GND GND GND VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AGND NPECL1 I/O / GL2 APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD GND GND GND GND GND VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AGND NPECL1 I/O / GL2 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15
624-Pin CCGA/LGA Pin Number M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 N1 N2 N3 N4 N5 APA600 Function I/O / GLMX1 VDDP GND VDD GND GND GND GND GND VDD GND VDDP I/O / GLMX2 I/O / GL4 NPECL2 AGND I/O I/O I/O I/O I/O I/O AVDD PPECL1 / Input I/O / GL1 I/O VDDP GND VDD GND GND GND GND GND APA1000 Function I/O / GLMX1 VDDP GND VDD GND GND GND GND GND VDD GND VDDP I/O / GLMX2 I/O / GL4 NPECL2 AGND I/O I/O I/O I/O I/O I/O AVDD PPECL1 / Input I/O / GL1 I/O VDDP GND VDD GND GND GND GND GND
v5.7
2-81
ProASICPLUS Flash Family FPGAs
624-Pin CCGA/LGA Pin Number N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 APA600 Function VDD GND VDDP I/O I/O / GL3 PPECL2 / Input AVDD I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDDP GND VDD GND GND GND GND GND VDD GND VDDP I/O I/O I/O GND I/O I/O APA1000 Function VDD GND VDDP I/O I/O / GL3 PPECL2 / Input AVDD I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VDDP GND VDD GND GND GND GND GND VDD GND VDDP I/O I/O I/O GND I/O I/O
624-Pin CCGA/LGA Pin Number P25 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T1 T2 T3 T4 T5 T6 T7 T8 T9 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD GND GND GND GND GND VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND VDD GND GND GND GND GND VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND
624-Pin CCGA/LGA Pin Number T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 APA600 Function VDD VDD VDD VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VDDP GND GND GND GND GND GND GND GND GND VDDP I/O APA1000 Function VDD VDD VDD VDD VDD VDD VDD GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VDDP GND GND GND GND GND GND GND GND GND VDDP I/O
2 -8 2
v5.7
ProASICPLUS Flash Family FPGAs
624-Pin CCGA/LGA Pin Number U20 U21 U22 U23 U24 U25 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 W1 W2 W3 W4 APA600 Function GND I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP RCK I/O I/O I/O GND I/O I/O I/O I/O I/O I/O APA1000 Function GND I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP RCK I/O I/O I/O GND I/O I/O I/O I/O I/O I/O
624-Pin CCGA/LGA Pin Number W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O
624-Pin CCGA/LGA Pin Number Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 APA600 Function I/O I/O GND I/O TCK VPP VPN I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI TRST I/O I/O I/O APA1000 Function I/O I/O GND I/O TCK VPP VPN I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI TRST I/O I/O I/O
v5.7
2-83
ProASICPLUS Flash Family FPGAs
624-Pin CCGA/LGA Pin Number AA25 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O GND I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD GND I/O I/O I/O GND I/O I/O
624-Pin CCGA/LGA Pin Number AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 APA600 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VDD I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O APA1000 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VDD I/O VDDP GND VDD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
624-Pin CCGA/LGA Pin Number AD20 AD21 AD22 AD23 AD24 AD25 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 APA600 Function I/O I/O I/O VDD GND VDDP GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND APA1000 Function I/O I/O I/O VDD GND VDDP GND VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDP GND
2 -8 4
v5.7
ProASICPLUS Flash Family FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version v5.6 (August 2008) v5.5 (February 2007) v5.4 (October 2006) Changes in current version (v5.7) VOH and VOL data in Table 1-22 was changed back to the data in v5.5. VOH and VOL data was updated in Table 1-22. Page page 1-38 page 1-38
A statement about single cell and cascaded cell timing diagrams was added to the "Enclosed page 1-65 Timing Diagrams - FIFO Mode:" section. The following pins were updated in the "144-FBGA Pin" table: Pin Number Updated Function C2 I/O / GL1 F1 I/O / GL2 page 2-38
v5.3 (May 2006)
The heading, MIL-STD-883B, and note 4 were added to the "Device Resources" table.
page iii
The "Temperature Grade Offerings" table was updated to include the military (M) temperature page iv grade in the following device/packages: APA300-FG144 APA300-FG256 APA600-FG256 APA600-FG484 APA600-FG676 APA1000-FG896 90 and 270 phase shift support was removed from the datasheet. The "Ordering Information" section was updated to include RoHS information. The last paragraph of the "Boundary Scan (JTAG)" section was updated. The Output Frequency Range in the "Timing Control and Characteristics" section. The title for Table 1-18 was updated. The caption was updated in Figure 1-48. N/A page ii page 1-11 page 1-13 page 1-34 page 1-72 N/A N/A page 1-20 page 2-6
v5.2 (December 2005)
v5.1
MIL-STD-883 was added to the datasheet. VCC and VCCI were changed to VDDP. Table 1-9 was updated to include 135C.
v5.0
In the "208-Pin PQFP" table, the following pin numbers have been updated: Pin Number Function 24 I/O / GL2 30 I/O / GL1 In the "208-Pin CQFP" table, the following pin numbers have been updated: Pin Number Function 23 I/O / GLMX1 24 I/O / GL2 28 PPECL1 / Input 30 I/O / GL1 128 I/O / GL3 129 PPECL2 / Input 134 I/O / GL4 135 I/O / GLMX2
v5.7
page 2-13
3-1
ProASICPLUS Flash Family FPGAs
Previous version v4.1
Changes in current version (v5.7) In the "624-Pin CCGA/LGA" table, the following pin numbers have been updated: Pin Number Function M6 I/O / GL2 M7 I/O / GLMX1 M19 I/O / GLMX2 M20 I/O / GL4 N5 PPECL1 / Input N6 I/O / GL1 N20 I/O / GL3 N21 PPECL2 / Input MIL-STD 883B data will be added into this datasheet after the MIL-STD 883B qualification is complete. Green packaging information in the "Ordering Information" section was updated. The "Temperature Grade Offerings" table was updated for the CG624. The "Ordering Information" section was updated. The "Live at Power-Up" section is new. Note 2 in Figure 1-4 was updated. The 3.3 V column in Table 1-3 was updated. The "Input/Output Blocks" section was updated. The note was removed from Table 1-4. The "Power-Up Sequencing" section was updated. The first bullet in the "ProASICPLUS Clock Management System" section was updated. The first paragraph in the "Performance Retention" section was updated. Mixed Voltage was removed from Table 1-19. Table 1-20 was updated. page ii
Page page 2-79
page iv page ii page 1-3 page 1-4 page 1-9 page 1-9 page 1-9 page 1-10 page 1-13 page 1-33 page 1-35 page 1-35
Mixed Mode Voltage was removed from Table 1-21 and the Military/MIL-STD-883B column was page 1-36 updated. All tables from page 1-42 to page 1-51 were updated. Table 1-48 is new. Figure 1-30 is new. Note 1 in Table 1-50 was updated. The notes in Table 1-54 were updated. A note was added to Figure 1-48. A note was added to Table 1-66. The "TRST Test Reset Input" section was updated in the "Pin Description" section. page 1-42 to page 1-51 page 1-53 page 1-53 page 1-55 page 1-59 page 1-72 Table 1-66 page 1-73
The "624-Pin CCGA/LGA" section was updated for the APA600 and APA1000. Please review all page 2-78 pin data. v4.0 Figure 1-20 was updated. Table 1-46 was updated. The "1152-Pin FBGA" figure was updated. Pin names were changed to more accurately reflect the multiple functions supported by each pin. page 1-19 page 1-52 page 2-69
3 -2
v5.7
ProASICPLUS Flash Family FPGAs
Previous version v3.5
Changes in current version (v5.7) The ProASICPLUS and ProASICPLUS Military/Aerospace datasheets were combined. This document now supports Commercial, Industrial, and Military Temperature devices. Table 1 was updated. The "Ordering Information" section was updated. "Plastic Device Resources" table was updated. The "Calculating Typical Power Dissipation" section was updated. "Performance Retention" section Table 1-18 Table 1-20 was updated. Table 1-21 was updated. Table 1-22 was updated. Table 1-46 was updated.
Page
page i-i page i-ii page i-ii page 1-30 page 1-33 page 1-34 page 1-35 page 1-36 page 1-38 page 1-52 page i-iv page i-iv page 1-13 page 1-16 page 1-21 page 1-22 page 1-27 page 1-29 page 1-65 page 1-73 page 2-4
The Long Term Jitter Peak-to-Peak Max. in the "PLL Electrical Specifications" table was updated. page 1-21
v3.4
The "Temperature Grade Offerings" table is new. The "Speed Grade and Temperature Matrix" table is new. The "ProASICPLUS Clock Management System" section was updated. The "Lock Signal" section was updated. The "PLL Electrical Specifications" table was updated. The "User Security" section was updated. The "Design Environment" section was updated. Table 1-15 was updated. The "Asynchronous FIFO Full and Empty Transitions" section was updated. The "AVDD PLL Power Supply" section in the "Pin Description" section was updated.
v3.3
The "144-Pin TQFP" table on page 2-4 was updated. The following pins changed: Pin 15 = GLMX1 Pin 16 = GL1 Pin 21 = GL2 Pin 88 = GL3 Pin93 = GL4 Pin 94 = GLMX2 The "ProASICPLUS Clock Management System" section was updated. Figure 1-14 was updated. Table 1-7 is new. Figure 1-20 was updated. The "PLL Electrical Specifications" section was updated. Figure 1-26 was updated. In the "Calculating Typical Power Dissipation" section, P9 was changed to 7.5 mW. The "Programming, Storage, and Operating Limits" section was updated. The "Recommended Design Practice for VPN/VPP" section was updated.
v3.2
page 1-13 page 1-14 page 1-15 page 1-19 page 1-21 page 1-42 page 1-30 page 1-33 page 1-74
v3.1 v3.0
The datasheet was updated to include references to guidelines concerning the use of certain ProASICPLUS I/O standards. In Table 1-2 on page 1-8, the Memory Rows - Bottom coordinates were changed. Figure 1-8 was updated. The VIL Minimum in the Table 1-22 was changed from 0.3 to -0.3. In the "Output Buffer Delays" section, the OB25LPLL tDHL Standard changed to 5.3. page 1-8 page 1-8 page 1-38 page 1-44
In the "Sample Macrocell Library Listing" section, the AND2 Standard maximum changed to 0.7 page 1-51 and the -F maximum changed to 0.8.
v5.7
3-3
ProASICPLUS Flash Family FPGAs
Previous version v2.0
Changes in current version (v5.7) The Table 1 was updated. The "Ordering Information" section was updated. The "Plastic Device Resources" section was updated. The "ProASICPLUS Architecture" section was updated. Table 1-2 was updated. Table 1-8 is new. Figure 1-11 is new.
Page page i-i page i-ii page i-ii page 1-2 page 1-8 page 1-16 page 1-10
The Introduction section in the "ProASICPLUS Clock Management System" section was page 1-13 updated. The "Physical Implementation" section was updated. The "Functional Description" on page 1-13 was updated. Figure 1-14 on page 1-14 through Figure 1-20 on page 1-19 were updated. The "PLL Electrical Specifications" on page 1-21 was updated. Figure 1-25 on page 1-26 was updated. The "Calculating Typical Power Dissipation" on page 1-30 was updated. The 'Nominal Supply Voltages' section was updated. The Table 1-22 was updated. The "Tristate Buffer Delays" on page 1-42 was updated. The "Output Buffer Delays" on page 1-44 was updated. The"Input Buffer Delays" on page 1-46 was updated. "Global Routing Skew" on page 1-50 was updated. The"Sample Macrocell Library Listing" on page 1-51 was updated. The "Pin Description" on page 1-73 was updated. The following pins have been changed in the "100-Pin TQFP" table: Pin Number Function Pin Number Function 10 I/O (GLMX1) 60 GL3 11 GL1 61 PPECL2 (I/P) 13 NPECL1 63 NPECL2 15 PPECL1(I/P) 65 GL4 16 GL2 66 I/O (GLMX2) "144-Pin TQFP" section is new. The following pins have been changed in the "208-Pin PQFP" table: Pin Number Function Pin Number Function 23 I/O (GLMX1) 128 GL3 24 GL1 129 PPECL2 (I/P) 26 NPECL1 132 NPECL2 28 PPECL1 (I/P) 134 GL4 30 GL2 135 I/O (GLMX2) The following pins have been changed in the "456-Pin PBGA" table: Pin Number Function Pin Number Function M1 GL1 N22 NPECL2 M2 GL2 N23 GL3 M22 GL4 N25 I/O (GLMX2) N2 I/O (GLMX1) P5 NPECL1 N4 PPECL1 (I/P) P26 PPECL2 (I/P) page 1-13 page 1-13 page 1-14 to page 1-19 page 1-21 page 1-26 page 1-30 page 1-34 page 1-38 page 1-42 page 1-44 page 1-46 page 1-50 page 1-51 page 1-73 page 2-1
page 2-3 page 2-5
page 2-22
3 -4
v5.7
ProASICPLUS Flash Family FPGAs
Previous version v2.0 (continued)
Changes in current version (v5.7) The following pins have been changed in the "144-Pin FBGA" table: Pin Number Function Pin Number Function C2 GL2 F9 GL4 D12 I/O (GLMX2 )F11 PPECL2 (I/P E11 NPECL2 F12 GL3 F1 GL1 G1 PPECL1 (I/P) F3 I/O (GLMX1) G4 NPECL1 The following pins have been changed in the "256-Pin FBGA" table: Pin Number Function Pin Number Function H1 GL1 H16 GL4 H2 NPECL1 J1 GL2 H3 I/O (GLMX1) J2 PPECL1 (I/P) H13 I/O (GLMX2) J13 PPECL2 (I/P) H14 NPECL2 J16 GL3 The following pins have been changed in the "484-Pin FBGA" table: Pin Number Function Pin Number Function L4 GL1 L19 GL4 L5 NPECL1 M4 GL2 L6 I/O (GLMX1) M5 PPECL1 (I/P) L16 I/O (GLMX2) M16 PPECL2 (I/P) L17 NPECL2 M19 GL3 The following pins have been changed in the "676-Pin FBGA" table: Pin Number Function Pin Number Function N1 GL1 N25 GL4 N3 I/O (GLMX1) P1 GL2 N5 NPECL1 P5 PPECL1 (I/P) N22 GL3 P22 I/O (GLMX2) N24 NPECL2 P24 PPECL2 (I/P) The following pins have been changed in the "896-Pin FBGA" table: Pin Number Function Pin Number Function R2 I/O (GLMX1) T3 GL2 R4 NPECL1 T4 PPECL1 (I/P) R5 GL1 T26 PPECL2 (I/P) R27 NPECL2 T27 GL4 R29 I/O (GLMX2) T28 GL3 The following pins have been changed in the "1152-Pin FBGA" table: Pin Number Function Pin Number Function U4 I/O (GLMX1) U29 NPECL2 U6 NPECL1 U31 I/O (GLMX2) U7 GL1 V28 PPECL2 (I/P) V5 GL2 V29 GL4 V6 PPECL1 (I/P) V30 GL3
Page page 2-37
page 2-40
page 2-45
page 2-51
page 2-59
page 2-69
v5.7
3-5
ProASICPLUS Flash Family FPGAs
Previous version Advanced v0.7
Changes in current version (v5.7) The "ProASICPLUS Architecture" section was updated. The "Array Coordinates" section and Table 1-2 are new. The "Power-Up Sequencing" section is new. "I/O Features" section was updated.
Page page 1-2 page 1-8 page 1-10 page 1-9
The "Timing Control and Characteristics" section was updated. "Physical Implementation" page 1-13 to page section, "Functional Description" section, "Lock Signal" section, and "PLL Configuration 1-16 Options" section are new. "PLL Block - Top-Level View and Detailed PLL Block Diagram" section was updated. Figure 1-15 was updated. page 1-14 page 1-15
"Sample Implementations" section, "Adjustable Clock Delay" section, and the "Clock Skew page 1-16 Minimization" section are new. Figure 1-16, Figure 1-17, Figure 1-18, Figure 1-19, and Figure 1-20 are new. The "PLL Electrical Specifications" section is new. The "Design Environment" section was updated. Figure 1-26 was updated. The "Calculating Typical Power Dissipation" section was updated. The "DC Electrical Specifications (VDDP = 2.5 V 0.2V)" section was updated. The Table 1-22 was updated. The "DC Specifications (3.3 V PCI Operation)1" section was updated. The "Tristate Buffer Delays" section (the figure and table) have been updated. The "Output Buffer Delays" section (the figure and table) have been updated. The "Input Buffer Delays" section was updated. The "Global Input Buffer Delays" section was updated. The "Predicted Global Routing Delay" section was updated. The "Global Routing Skew" section was updated. The "Sample Macrocell Library Listing" section was updated. The "Pin Description" section was updated. GLMX is new. The "Recommended Design Practice for VPN/VPP" section was updated. Pin AK31 of FG1152 for the APA1000 changed to VPP. (Advanced v0.6) The "Features and Benefits" on page i-i were updated. The "ProASICPLUS Product Profile" on page i-i was updated. The "Ordering Information" on page i-ii was updated. The "Plastic Device Resources" on page i-ii was updated. The "ProASICPLUS Architecture" on page 1-2 was updated. Table 1-1 was updated. Figure 1-14 was updated. The "Design Environment" section was updated. The "Package Thermal Characteristics" section was updated. The "Calculating Typical Power Dissipation" section was updated. The "Absolute Maximum Ratings*" section was updated. The "Programming, Storage, and Operating Limits" section was updated. The 'Nominal Supply Voltages' section was updated. The "Recommended Operating Conditions" section was updated. The "DC Electrical Specifications (VDDP = 2.5 V 0.2V)" section was updated. page 1-17 to page 1-19 page 1-21 page 1-27 page 1-42 page 1-30 page 1-36 page 1-38 page 1-40 page 1-42 page 1-44 page 1-46 page 1-48 page 1-50 page 1-50 page 1-51 page 1-73 page 1-74 page 2-69 page i-i page i-i page i-ii page i-ii page 1-2 page 1-7 page 1-14 page 1-27 page 1-29 page 1-30 page 1-33 page 1-33 page 1-34 page 1-35 page 1-36
The "DC Electrical Specifications (VDDP = 3.3 V 0.3 V and VDD = 2.5 V 0.2 V)" section was page 1-38 updated.
3 -6
v5.7
ProASICPLUS Flash Family FPGAs
Previous version
Changes in current version (v5.7) The "Synchronous Write and Read to the Same Location" section was updated. The "Asynchronous FIFO Read" section was updated. The "Pin Description" section has been updated. The "Recommended Design Practice for VPN/VPP" section is new. The "100-Pin TQFP" section is new. The "484-Pin FBGA" section is new.
Page page 1-61 page 1-67 page 1-73 page 1-74 page 2-1 page 2-45 page 1-74 page i-ii page 1-14 page 1-42 page 1-44 page 1-46 page 1-48 page 2-22 page 2-51 page i-i page i-ii page 1-9
Advanced v0.6 (continued)
The "Asynchronous Write and Synchronous Read to the Same Location" section was updated. page 1-62
Advanced v0.5 Advanced v0.4
The description for the VPN pin has changed. The "Plastic Device Resources" section has been updated. Figure 1-12 and Figure 1-13 have been updated. The "Tristate Buffer Delays" section has been updated. The "Output Buffer Delays" section has been updated. The "Input Buffer Delays" section has been updated. The "Global Input Buffer Delays" section has been updated. The "456-Pin PBGA" section has been updated. The "676-Pin FBGA" section has been updated.
Advanced v0.3
The "ProASICPLUS Product Profile" section has been changed. The "Plastic Device Resources" section has been updated. The "ProASICPLUS I/O Power Supply Voltages" sectionhas been updated. WDATA has ben changed to DI, and RDATA has been changed to DO to make them consistent with the signal names found in the Macro Library Guide. Figure 1-21 and Figure 1-22 have been updated. The "Design Environment" section and Figure 1-26 have been updated. The table in the "Package Thermal Characteristics" section has been updated. The "Calculating Typical Power Dissipation" section is new. The "Programming, Storage, and Operating Limits" section is new. The 'Nominal Supply Voltages' section has been updated. The "DC Electrical Specifications (VDDP = 2.5 V 0.2V)" section was updated.
page 1-24 and page 1-25 page 1-27 and page 1-42 page 1-29 page 1-30 page 1-33 page 1-34 page 1-36
The "DC Electrical Specifications (VDDP = 3.3 V 0.3 V and VDD = 2.5 V 0.2 V)" section was page 1-38 updated. The "Recommended Operating Conditions" section was updated. The "ProASICPLUS Clock Management System" section was updated. Figure 1-14 was updated. page 1-35 page 1-13 page 1-14 page 1-12 page 1-24 page 1-25
Advanced v0.3 (continued)
Figure 1-13 is new. Tables 5, 6, and 7 from Advanced v0.3 were removed. The "Memory Block SRAM Interface Signals" section was updated. The "Memory Block FIFO Interface Signals" section was updated. All pinout tables have been updated, and several packages are new: 208-Pin PQFP - APA150, APA300, APA450, APA600 456-Pin PBGA - APA150, APA300, APA450, APA600 144-Pin FBGA - APA150, APA300, APA450 256-Pin FBGA - APA150, APA300, APA450, APA600 676-Pin FBGA - APA600
Advanced v0.1
Figure 1-23 has been updated.
page 1-26
v5.7
3-7
ProASICPLUS Flash Family FPGAs
Data Sheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families.
Export Administration Regulations (EAR)
The products described in this datasheet are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
3 -8
v5.7
Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.
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Price & Availability of APA1000-FLGGB

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